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ARM920T PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ARM920T
기능 System-on-Chip Platform OS Processor
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ARM920T 데이터시트, 핀배열, 회로
®
Product Overview
ARM920T
System-on-Chip Platform OS Processor
Applications
• Applications running a
platform OS:
- EPOC
- Linux
- WindowsCE
• High performance wireless
applications:
- Smart phones
- PDAs
• Networking applications
• Digital set top boxes
• Imaging
• Automotive control
solutions
• Audio and video encoding
and decoding
Benefits
• Designed specifically for
System-On-Chip
integration
• Supports the Thumb
instruction set offering the
same excellent code
density as the ARM7TDMI.
• High performance allows
system designers to
integrate more functionality
into price and
power-sensitive
applications demanding
more performance
• Cached processor with an
easy to use lower
frequency on-chip system
bus interface.
The ARM920T™
The ARM920T is a a high-performance 32-bit RISC integer processor
macrocell combining an ARM9TDMI™ processor core with:
• 16KB instruction and 16KB data caches
• instruction and data Memory Management Units (MMUs)
• write buffer
• an AMBA™ (Advanced Microprocessor Bus Architecture) bus interface
• an Embedded Trace Macrocell (ETM) interface.
High performance
The ARM920T provides a high-performance processor solution for open
systems requiring full virtual memory management and sophisticated memory
protection. An enhanced ARM® architecture version 4 MMU implementation
provides translation and access permission checks for instruction and data
addresses.
The ARM920T high-performance processor solution gives considerable
savings in chip complexity and area, chip system design, and power
consumption.
Compatible with ARM7™ and StrongARM®
The ARM920T processor is 100% user code binary compatible with
ARM7TDMI and backwards compatible with the ARM7 Thumb® Family and
the StrongARM processor families, giving designers software-compatible
processors with a range of price/performance points from 60 MiPS to 200+
MIPS. Support for the ARM architecture today includes:
• WindowsCE, EPOC, Linux, and QNX operating systems
• 40+ Real Time Operating Systems
• cosimulation tools from leading EDA vendors
• variety of software development tools.
.
DVI 0024A
© Copyright ARM Limited 2000. All rights reserved.
ARM Confidential - Draft
Page 1




ARM920T pdf, 반도체, 판매, 대치품
The ARMv4T Architecture
Registers
The ARM9TDMI processor core
consists of a 32-bit datapath and
associated control logic. That
datapath contains 31 general-
purpose registers, coupled to a full
shifter, Arithmetic Logic Unit, and
multiplier. At any one time 16
registers are visible to the user. The
remainder are synonyms used to
speed up exception processing.
Register 15 is the Program Counter
(PC) and can be used in all
instructions to reference data relative
to the current instruction. R14 holds
the return address after a subroutine
call. R13 is used (by software
convention) as a stack pointer.
Modes and exception
handling
All exceptions have banked registers
for R14 and R13. After an exception,
R14 holds the return address for
exception processing. This address
is used both to return after the
exception is processed and to
address the instruction that caused
the exception. R13 is banked across
exception modes to provide each
exception handler with a private
stack pointer. The fast interrupt mode
also banks registers 8 to 12 so that
interrupt processing can begin
without the need to save or restore
these registers. A seventh
processing mode, System mode,
does not have any banked registers.
It uses the User mode registers.
System mode runs tasks that require
a privileged processor mode and
allows them to invoke all classes of
exceptions.
Status registers
All other processor states are held in
status registers. The current
operating processor status is in the
Current Program Status Register
(CPSR). The CPSR holds:
• four ALU flags (Negative, Zero,
Carry, and Overflow),
• two interrupt disable bits (one for
each type of interrupt),
• a bit to indicate ARM or Thumb
execution,
• and five bits to encode the
current processor mode.
All five exception modes also have a
Saved Program Status Register
(SPSR) which holds the CPSR of the
task immediately before the
exception occurred.
Exception types
ARM9TDMI supports five types of
exception, and a privileged
processing mode for each type. The
types of exceptions are:
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to
implement memory protection or
virtual memory)
• attempted execution of an
undefined instruction
• software interrupts (SWIs).
Conditional execution
All ARM instructions (with the
exception of BLX) are conditionally
executed. Instructions optionally
update the four condition code flags
(Negative, Zero, Carry, and
Overflow) according to their result.
Subsequent instructions are
conditionally executed according to
the status of flags. Fifteen conditions
are implemented.
Four classes of
instructions
The ARM and Thumb instruction sets
can be divided into four broad
classes of instruction:
• data processing instructions
• load and store instructions
• branch instructions
• coprocessor instructions.
Data processing
The data processing instructions
operate on data held in general
purpose registers. Of the two source
operands, one is always a register.
The other has two basic forms:
• an immediate value
• a register value optionally
shifted.
If the operand is a shifted register the
shift amount might have an
immediate value or the value of
another register. Four types of shift
can be specified. Most data
processing instructions can perform
a shift followed by a logical or
arithmetic operation. Multiply
instructions come in two classes:
• normal - 32-bit result
• long - 32-bit result variants.
Both types of multiply instruction can
optionally perform an accumulate
operation.
Load and store
The second class of instruction is
load and store instructions. These
instructions come in two main types:
• load or store the value of a single
register
• load and store multiple register
values.
Page 4
© Copyright ARM Limited 2000. All rights reserved.
ARM Confidential - Draft
DVI 0024A

4페이지










ARM920T 전자부품, 판매, 대치품
The ARMv4T Architecture
The Thumb instruction set
Mnemonic
MOV
ADD
SUB
RSB
CMP
TST
AND
EOR
LSL
ASR
MUL
B
BL
BX
LDR
LDRH
LDRB
LDRSH
LDMIA
PUSH
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Logical Shift Left
Arithmetic Shift Right
Multiply
Unconditional Branch
Branch and Link
Branch and Exchange
Load Word
Load Halfword
Load Byte
Load Signed Halfword
Load Multiple
Push Registers to stack
Mnemonic
MVN
ADC
SBC
RSC
CMN
NEG
BIC
ORR
LSR
ROR
BKPT
Bcc
BLX
SWI
STR
STRH
STRB
LDRSB
STMIA
POP
Operation
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Negate
Bit Clear
Logical (inclusive) OR
Logical Shift Right
Rotate Right
Breakpoint
Conditional Branch
Branch and Link and Exchange
Software Interrupt
Store Word
Store Halfword
Store Byte
Load Signed Byte
Store Multiple
Pop Registers from stack
DVI 0024A
© Copyright ARM Limited 2000. All rights reserved.
ARM Confidential - Draft
Page 7

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System-on-Chip Platform OS Processor

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