PDF AS4LC4M16S0-10TC Data sheet ( Hoja de datos )

Número de pieza	AS4LC4M16S0-10TC
Descripción	3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Fabricantes	ETC
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Advance information AS4LC8M8S0 AS4LC4M16S0 ® 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM Features • PC100/133 compliant • Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16) • Fully synchronous - All signals referenced to positive edge of clock • Four internal banks controlled by BA0/BA1 (bank select) • High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time • Low power consumption - Standby: 7.2 mW max, CMOS I/O • 4096 refresh cycles, 64 ms refresh interval • Auto refresh and self refresh • Automatic and direct precharge • Burst read, single write operation • Can assert random column address in every cycle • LVTTL compatible I/O • 3.3V power supply • JEDEC standard package, pinout and function - 400 mil, 54-pin TSOP II • Read/write data masking • Programmable burst length (1/2/4/8/full page) • Programmable burst sequence (sequential/interleaved) • Programmable CAS latency (2/3) Pin arrangement AS4LC4M16S0 VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 VSS VSS 53 DQ15 DQ7 52 VSSQ VSSQ 51 DQ14 NC 50 DQ13 DQ6 49 VCCQ VCCQ 48 DQ12 NC 47 DQ11 DQ5 46 VSSQ VSSQ 45 DQ10 NC 44 DQ9 DQ4 43 VCCQ VCCQ 42 DQ8 NC 41 VSS 40 NC VSS NC 39 UDQM DQM 38 CLK CLK 37 CKE CKE 36 NC 35 A11 NC A11 34 A9 33 A8 A9 A8 32 A7 31 A6 30 A5 A7 A6 A5 29 A4 28 VSS A4 VSS AS4LC4M16S0 Pin designation Pin(s) DQM (8M×8) UDQM/LDQM (4M×16) A0 to A11 BA0, BA1 DQ0 to DQ7 (8M×8) DQ0 to DQ15 (4M×16) RAS CAS WE CS VCC, VCCQ VSS, VSSQ CLK CKE Description Output disable/write mask Address inputs Bank select inputs Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable Selection guide Bus frequency CL = 2 Minimum clock access time CL = 3 Minimum setup time Minimum hold time Minimum RAS to CAS delay Minimum RAS precharge time Remarks: (CL/tRCD/tRP) Symbol fmax tAC tAC tS tH tRCD tRP -75 (PC133) 133 – 5.4 1.5 0.8 3 3 3/3/3 -8 125 – 6 2 1.0 3 3 3/3/3 -10F (PC100) 100 6 – 2 1.0 2 2 2/2/2 -10 (PC100) 100 – 6 2 1.0 3 3 3/3/3 Unit MHz ns ns ns ns cycles cycles 7/5/00 ALLIANCE SEMICONDUCTOR 1 Copyright ©2000 Alliance Semiconductor. All rights reserved. 1 page Mode register fields Address Function † RFU = 0 during MRS cycle. Write burst length A9 Length 0 Programmed burst length 1 Single burst AS4LC8M8S0 AS4LC4M16S0 ® Register programmed with MRS A11~A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU† WBL TM CAS latency BT Burst length Burst type A3 Type 0 Sequential 1 Interleaved Test mode A8 A7 Type 0 0 Mode register set 01 Reserved 10 Reserved 11 Reserved CAS latency A6 A5 A4 Latency 00 0 Reserved 00 1 Reserved 01 0 2 01 1 3 1X X Reserved Burst length A2 A1 A0 BT = 0 BT = 1 0 00 1 1 0 01 2 2 0 10 4 4 0 11 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full page Reserved 7/5/00 ALLIANCE SEMICONDUCTOR 5 5 Page AS4LC8M8S0 AS4LC4M16S0 ® Device operation (continued) Command Pin Settings Description Burst stop CS = WE = low; RAS = Use burst stop to terminate burst operation. This command may be used CAS = high to terminate all legal burst lengths. Bank precharge CS = A10 = RAS = WE = low; CAS = high; A11 = bank select; A0~A9 = don’t care The Bank Precharge command precharges the bank specified by BA0 and BA1. The precharged bank is switched from active to idle state and is ready to be activated again. Assert the precharge command after tRAS(min) of the bank activate command in the specified bank. The precharge operation requires a time of tRP(min) to complete. CS = RAS = WE = low; Precharge all CAS = A10 = high; The Precharge All command precharges all four banks simultaneously. BA0~BA1 = bank select; All four banks are switched to the idle state on precharge completion. A0~A9 = don’t care CS = CAS = WE (write) = During auto precharge, the SDRAM adjusts internal timing to satisfy low; RAS = WE (read) = tRAS(min) and tRP for the programmed CAS latency and burst length. A10 = high; BA0~BA1 = Couple the auto precharge with a burst read/write operation by Auto precharge bank select; A0~A9 = asserting A10 to a high state at the same time the burst read/write column address; (A9 = commands are issued. At auto precharge completion, the specified bank don’t care for 2M×8; is switched from active to idle state. Note that no new commands to the A8,A9 = don’t care for bank can be issued until the specified bank achieves the idle state. Auto 1M×16) precharge doesn’t work with full-page burst. When CKE is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. Clock suspend/power down mode entry CKE = low If all banks are idle and CKE goes low, the SDRAM enters power down mode at the next clock cycle. When in power down mode, no input commands are acknowledged as long as CKE remains low. To exit power down mode, raise CKE high before the rising edge of CLK. Clock suspend/power down mode exit CKE = high Resume internal clock operation by asserting CKE high before the rising edge of CLK. Subsequent commands can be issued one clock cycle after the end of the Exit command. SDRAM storage cells must be refreshed every 64ms to maintain data integrity. Use the Auto Refresh command to refresh all rows in all banks of the SDRAM. The row address is provided by an internal counter Auto refresh CS = RAS = CAS = low; WE = CKE = high; A0~A11 = don’t care which increments automatically. Auto refresh can only be asserted when all four banks are idle and the device is not in the power down mode. The time required to complete the auto refresh operation is tRC(min). Use NOPs in the interim until the auto refresh operation is complete. This is the most common refresh mode. It is typically performed once every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. All four banks will be in the idle state after this operation. Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh address and timing are provided internally. Self refresh entry is allowed only when all four banks are idle. The internal clock and all CS = RAS = CAS = CKE = input buffers with the exception of CKE are disabled in this mode. Exit Self refresh low; WE = high; A0~A11 self refresh by restarting the external clock and then asserting CKE high. = don’t care NOP’s must follow for a time of tRC(min) for the SDRAM to reach the idle state where normal operation is allowed. If burst auto refresh is used in normal operation, burst 4096 auto refresh cycles immediately after exiting self refresh. 7/5/00 ALLIANCE SEMICONDUCTOR 11 11 Page

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