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PDF AS5501 Data sheet ( Hoja de datos )
| Número de pieza | AS5501 | |
| Descripción | Multimode Powerline-Modem | |
| Fabricantes | austriamicrosystems AG | |
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AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
AS5501 / AS5502
Multimode Powerline-Modem
Data Sheet
Rev A
1 page  
AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
1.1 SERIF, RESET, TIMING
Default Setting Rom
A0/CS
SD-IN
SCLK
SERIAL INTERFACE
CONTROL REGISTERS
SD-OUT
Control Register Output
RES-TH
POR
BD1,2, ZCEN, MMV
MCLK
TXEN
ZC
TIMING
RESN
BAND GAP REF.
VREF
TXENI
CKTX
SC-CLK
Fmixer
mux
Mclk/2
CKSYS
IF-SCCLK
Test1,2
1.1.1 SERIAL INTERFACE
There is a serial interface implemented for setting the control bits by a CPU.
Three bytes are available with following definitions and default contents (after reset).
Reg.-Name addr D1 D2 D3 D4 D5 D6 D7 D8
MRK-REG 00H MRK1 MRK2 MRK3 MRK4 MRK5 MRK6 MRK7 MRK8
(def. value)
1 0 1 0 0 0 11
GLOBAL 01H MRK9
(def. value)
1
BD1
1
BD2 RxBw1 RxBw2 ZCEN MMV PWD
1 1 0 1 00
TEST
02H TEST1 TEST2 ASYN AgcH digMix noTSTin TxSyn FCdOn
(The default setting of the register "TEST" is always 00h.)
Bit-Name
Function
default val. default function
MRK1-9 defines TX Mark Frequency (63.9k-140.55kHz)
453
131.85kHz
BD1,2
defines Baud-Rate and Modulation-Depth
1, 1
2400Hz/1200Hz
RXBW1,2
defines RX-BandPassFilter Bandwidth
1, 0 4.8kHz @132.45kHz
ZCEN
disable ZeroCrossing TX-Sync
1 ZC-disabled
MMV
disables transmit Timeout
0 TimeOut enabled
PWD
enables power down mode
0 powered up
TEST1,2
enables Test Mode 1-3
0, 0 normal mode
ASYN
disable synchronized receive data RXD
0
sync. RXD
AgcH
hold AGC counter-state
0 AGC-loop active
digMix enables digital mixer; analog mixer enabled by def.
0
analog mixer
noTSTin TST-out function only for receiver debugging 0 TSTin&out availab.
TxSyn enables TXD sampling with CLR/T rising-edge
0 CLR/T gets synchronised
by TXD-edges
FCdOn
enables faster CD-ON timing (5/Bdrate)
0 Tcdon=(10/Bdrate)
Rev A, May 2000
Page 4/25
5 Page 
AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
To establish the frequency modulation, the output of the mark/space up/down-counter gets
added to Nmark. There has to be a smooth frequency-change from mark to space and from
space to mark within half the bit-time with 3 intermediate frequencies.
BD1 BD2 Fspace-Fmark Baud-Rate (CKTX) M/S-UDC BDclk (UDC-CLK)
00
600Hz
600Hz
0,1,2,3,4
4800Hz
10
1200Hz
1200Hz
0,2,4,6,8
9600Hz
01
600Hz
1200Hz
0,1,2,3,4
9600Hz
11
1200Hz
2400Hz
0,2,4,6,8
19200Hz
Example with MRK-REG=8 => Fmark=81.75kHz; BD1,2=0 => dF=BRate=600Hz:
BDR*8
TXD (H=mark)
(L=space)
N 545 546 547 548
549
Fsynth / 16
(kHz)
82.20
82.05
81.90
81.75
82.35
548 547 546 545
82.20
82.05
81.90
81.75
In receive-mode(TxEn=1), a constant number Nmix defined by BD1 gets added to Nmark
instead of the output of the M/S-UDC. This gives a constant frequency which is used as
Mixer-frequency to fold the FSK-signal down to 2.7kHz or 5.4kHz. According to the
mixer-frequency the IF-SC-CLK is defined by the timing-block (see 1.1.3).
BD1 BD2 IFcenter IFbandw IF-SC-CLK
Nmix BDclk (UDC-CLK)
0 X 2700Hz 1200Hz
57.6kHz
20
4800Hz
1 X 5400Hz 2400Hz
115.2kHz
40
9600Hz
The second frequency-synthesiser which is a similar structure as described for generating the
FSK-frequencies, is generating the target-frequency for the SCCLK-PLL. To get no
disturbing components, the phase-jitter of the synthesiser has to be reduced by the PLL.
There is a capacitor needed as external low-pass filter, to define the frequency response of the
PLL-loop. To generate the right target-frequency, one half of modulation-depth which is a
factor of 2 or 4 dependent on BD1 has to be added to Nmark. Since the center-frequency is a
very critical parameter, there is a possibility implemented for adjustment by wafersort-trim.
BD1 BD2 Fspace-Fmark (Fcenter-Fmark)/150Hz
Npll
0X
600Hz
2 MRK_REG + 426 + Itrim + 2
1 X 1200Hz
4 MRK_REG + 426 + Itrim + 4
(Itrim=0 ... 3 defined at wafer-sort)
Rev A, May 2000
Page 10/25
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AS5501.PDF ] | |
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