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PDF AM24LC08NA Data sheet ( Hoja de datos )
| Número de pieza | AM24LC08NA | |
| Descripción | 2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM | |
| Fabricantes | ETC | |
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2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM
ATC
AM24LC08
Features
•State- of- the- art architecture
- Non-volatile data storage
- Standard voltage and low voltage operation
(Vcc = 2.7V to 5.5V) for AM24LC08
• 2-wire I2C serial interface
- Provides bi-directional data transfer protocol
• 16-byte page write mode
- Minimizes total write time per word
• Self-timed write-cycle (including auto-erase)
• Durable and Reliable
- 40 years data retention
- Minimum of 1M write/erase cycles per word
- Unlimited read cycles
- ESD protection
• Low standby current
• Packages: PDIP-8L, SOP-8L
General Description
The AM24LC08 is a non-volatile, 8192-bit serial
EEPROM with conforms to all specifications in I2C 2
wire protocol. The whole memory can be disabled
(Write Protected) by connecting the WP pin to Vcc.
This section of memory then becomes unalterable
unless WP is switched to Vss. The AM24LC08
communication protocol uses CLOCK(SCL) and
DATA I/O(SDA) lines to synchronously clock data
between the master (for example a
microcomputer)and the slave EEPROM
devices(s) .In addition, the bus structure allows for a
maximum of 16K of EEPROM memory. This
supports the family in 2K, 4K, 8K devices, allowing
the user to configure the memory as the application
requires with any combination of EEPROMs (not to
exceed 16K).
Anachip EEPROMs are designed and tested for
application requiring high endurance, high reliability,
and low power consumption.
Connection Diagram
Pin Assignments
NC
NC
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PDIP / SOP
Name
NC
A2
VSS
SDA
SCL
WP
VCC
Description
No connect
Device address inputs
Ground
Data I/O
Clock input
Write protect
Power pin
Ordering Information
AM 24 LC 08 X X X
Operating Voltage
LC: 2.7~5.5V, CMOS
Type
08 =8K
Temp. grade
Blank
I
V
:
:
:
- -44000oooCCC~~~+++1782055oooCCC
Package
S: SOP-8L
N: PDIP-8L
Packing
Blank : Tube
A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.A1 Oct 20, 2003
1/10
1 page  
2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM
ATC
AM24LC08
Functional Description (Continued)
Devices Addressing
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit
device code (1010) for the AM24LC08, 3-bit device
address (A2 A1 A0) and 1-bit value indicating the
read or write mode. All I2C EEPROMs use and
internal protocol that defines a PAGE BLOCK size of
8K bits. The eighth bit of slave address determines if
the master device wants to read or write to the
AM24LC08. (Refer to table B).
The AM24LC08 monitor the bus for its
corresponding slave address all the time. It
generates an acknowledge bit if the slave address
was true and it is not in a programming mode.
Table B
Operation Control Code
Chip
R/W
Select
Read
1010
A2 A1 A0
1
Write
1010
A2 A1 A0
0
A2 are used to access device address for
AM24LC08; A0, A1 are no connect.
Write Operations
Byte Write
Following the start signal from the master, the slave
address is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow
after it has generated a acknowledge bit during the
ninth clock cycle.
Therefore the next byte transmitted by the master is
the word address and will be written into the address
pointer of the AM24LC08. After receiving another
acknowledge signal from the AM24LC08 the master
device will transmit the data word to be written into
the addressed memory location. The AM24LC08
acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this period the AM24LC08 will not
generate acknowledge signals. (Shown in Figure 4)
Page Write
The write control byte, word address and the first
data byte are transmitted to the AM24LC08 in the
same way as in a byte write. But instead of
generating a stop condition the master transmit up
to 16 data bytes to the AM24LC08 which are
temporarily stored in the on-chip page buffer and will
be written into the memory after the master has
transmitted a stop condition. After the receipt of
each byte, the four lower order address pointer bits
are internally incremented by one. The higher order
six bits of the word address remains constant. If the
master should transmit more than 16 bytes prior to
generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once
the stop condition is received an internal write cycle
will begin. (Shown in Figure 5).
Acknowledge Polling
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle
is complete (this feature can be used to maximize
bus throughout). Once the stop condition for a write
command has been issued from the master, the
device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves
the master sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle , then no ACK
will returned. If the cycle is complete then the device
will return the ACK and the master can then proceed
with the next read or write commands.
Write Protection
Programming will not take place if the WP pin of the
AM24LC08 is connected to Vcc. The AM24LC08 will
accept slave and byte addresses. But if the memory
accessed is write protected by the WP pin, the
AM24LC08 will not generate an acknowledge after
the first byte of data has been received, and thus the
programming cycle will not be started when the stop
condition is asserted.
Read Operations
Read operations are initiated in the same way as
write operations with the exception that the R/W bit
of the slave address is set to one. There are three
basic types of read operations: current address read,
random read, and sequential read.
Anachip Corp.
www.anachip.com.tw
5/10
Rev.A1 Sep 16, 2003
5 Page | ||
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