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PDF AM24LC21N Data sheet ( Hoja de datos )
| Número de pieza | AM24LC21N | |
| Descripción | Dual Mode/ 1K-bits (128 x 8) 2-Wire Serial EEPROM | |
| Fabricantes | ETC | |
| Logotipo |  |
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Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
AM24LC21
(Preliminary)
Features
- Single supply with operation down to 2.5V
- Completely implements DDC1/DDC2 interface for
monitor identification, including recovery to DDC1
- Low power CMOS technology
- 1 mA typical active current
- 10 uA standby current typical at 5.5V
- 2-wire serial interface bus, I2C compatible
- 100Khz (2.5V) and 400Khz (5V) compatibility
- Self-timed write cycle (including auto-erase)
- Hardware write-protect pin
- Page-write buffer for up to eight bytes
- 1,000,000 erase/write cycles
- Data retention > 40 years
- 8-pin PDIP and SOP packages
- Available for extended temperature ranges
Commercial (C): 0°C to +70°C
Industrial (I): -40°C to +85°C
General Description
The AM24LC21 is a 128 x 8-bit dual-mode
Electrically Erasable PROM. This device is
designed for use in applications requiring storage
and serial transmission of configuration and control
information. Two modes of operation have been
implemented: transmit only mode and bi-directional
mode. Upon power-up, the device will be in the
transmit only mode, sending a serial bit stream of
the memory array contents, clocked by the VCLK
pin. A valid high to low transition on the SCL pin will
cause the device to enter the bi-directional mode,
with byte selectable read/write capability of the
memory array. The AM24LC21 is available in a
standard 8-pin PDIP and SOP package in both
commercial and industrial temperature ranges.
Pin Assignments
(Top View)
NC
NC
WP
VSS
18
27
36
45
PDIP Package
VCC
VCLK
SCL
SDA
(Top View)
NC
NC
WP
VSS
18
27
36
45
SOP Package
VCC
VCLK
SCL
SDA
Pin Descriptions
Name
Description
NC No connection
VSS
Ground
SDA
Serial address/data I/O
VCLK Serial clock (transmit only mode)
VCC
SCL
Power supply
Serial clock (bi-directional mode)
WP Write protect (active low)
Note. See pin description (continued) for more detailed
Ordering Information
AM24LC 21 X X X
Operating Voltage
LC : 2.5V~5.5V,CMOS
Type
1K Dual Mode
Temp. grade
Blank : 0o C ~ +70o C
I : −40o C ~ +85o C
Package
S : SOP-8L
N : PDIP-8L
Packing
Blank : Tube
A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 0.0 Aug 10, 2002
1/13
1 page  
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
AM24LC21
(Preliminary)
Functional description
1.0 Overview
The AM24LC21 operates in two modes, the
transmit-only mode and the bi-directional mode.
There is a separate two wire protocol to support
each mode, each having a separate clock input and
sharing a common data line (SDA). The device
enters the Transmit-Only Mode upon power-up. In
this mode, the device transmits data bits on the
SDA pin in response to a clock signal on the VCLK
pin. The device will remain in this mode until a valid
high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the bi-directional mode. The
only way to switch the device back to the
transmit-only mode is to remove power from the
device.
2.1 Transmit-only mode
The device will power up in the transmit-only mode.
This mode supports a unidirectional two wire
protocol for trans-mission of the contents of the
memory array. This device requires that it be
initialized prior to valid data being sent in the
transmit-only mode (see Initialization Procedure,
below). In this mode, data is transmitted on the
SDA pin in 8 bit bytes, each followed by a ninth, null
bit (see Figure 2-1). The clock source for the
transmit-only mode is provided on the VCLK pin,
and a data bit is output on the rising edge on this
pin. The eight bits in each byte are transmitted most
significant bit first. Each byte within the memory
array will be output in sequence. When the last byte
in the memory array is transmitted, the output will
wrap around to the first location and continue. The
bi-directional mode clock (SCL) pin must be held
high for the device to remain in the transmit-only
mode.
2.2 Initialization procedure
After VCC has stabilized, the device will be in the
transmit-only mode. Nine clock cycles on the VCLK
pin must be given to the device for it to perform
internal synchronization. During this period, the
SDA pin will be in a high impedance state. On the
rising edge of the tenth clock cycle, the device will
output the first valid data bit which will be the most
significant bit of a byte. The device will power up at
an indeterminate byte address. (Figure 2-2).
SCL
SDA
TVAA
TVAA
BIT1(LSB)
NULL BIT
BIT8(MSB)
BIT7
VCLK
TVHIGH
TVLOW
Figure 2-1. Transmit only mode
VCC
SCL
SDA
VCLK
Anachip Corp.
www.anachip.com.tw
HIGH IMPEDANCE FOR 9 CLOCK CYCLES
TVPU
12
8
TVAA
TVAA
BIT8
BIT7
9 10 11
Figure 2-2. Device initialization
Rev 0.0 Aug 10, 2002
5/13
5 Page 
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
AM24LC21
(Preliminary)
Bus activity
Master
SDA Line
Bus activity
S
T
A
Control
Byte
R
T
S
Word
address
S
T Control
A Byte
R
T
S
Data(n)
S
T
O
P
P
AA
CC
KK
A
C
K
Figure 7-2. Random read
N
O
A
C
K
Bus activity
Master
SDA Line
Bus activity
Contro
Byte
Data(n)
Data(n+1)
Data(n+2)
A AAA
C CCC
K KKK
Figure 7-3. Sequential read
Data(n+X)
S
T
O
P
P
N
O
A
C
K
Pin Descriptions (Continued)
SDA
This pin is used to transfer addresses and data into
and out of the device, when the device is in the
bi-directional mode. In the transmit-only mode,
which only allows data to be read from the device,
data is also transferred on the SDA pin. This pin is
an open drain terminal, therefore the SDA bus
requires a pull-up resistor to VCC (typical 10k for
100 Khz, 1k for 400 Khz).
For normal data transfer in the bi-directional mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for
indicating the START and STOP conditions.
SCL
This pin is the clock input for the bi-directional
mode, and is used to synchronize data transfer to
and from the device. It is also used as the signaling
input to switch the device from the transmit only
mode to the bi-directional mode. It must remain
high for the chip to continue operation in the
transmit only mode.
VCLK
This pin is the clock input for the transmit only
mode. In the transmit only mode, each bit is
clocked out on the rising edge of this signal. In the
bi-directional mode, a high logic level is required on
this pin to enable write capability.
WP
When using the AM24LC21 in the bi-directional
Mode, the VCLK pin operates as the write protect
control pin. Setting VCLK high allows normal write
operations, while setting VCLK low prevents writing
to any location in the array. Connecting the VCLK
pin to VSS would allow the AM24LC21 to operate
as a serial ROM, although this configuration would
prevent using the device in the transmit-only mode.
If WP is connected to GND, PROGRAM operation
onto the whole memory will not be executed. READ
operation are possible. If WP is connected to Vcc,
normal memory operation is enabled,
READ/ WRITE over the entire memory is possible.
Anachip Corp.
www.anachip.com.tw
11/13
Rev 0.0 Aug 10, 2002
11 Page | ||
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