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PDF Am27C2048-55JI5 Data sheet ( Hoja de datos )
| Número de pieza | Am27C2048-55JI5 | |
| Descripción | 2 Megabit (128 K x 16-Bit) CMOS EPROM | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
Am27C2048
2 Megabit (128 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time
— Speed options as fast as 55 ns
s Low power consumption
— 100 µA maximum CMOS standby current
s JEDEC-approved pinout
— Plug-in upgrade of 1 Mbit EPROM
— 40-pin DIP/PDIP
— 44-pin PLCC
s Single +5 V power supply
s ±10% power supply tolerance standard
s 100% Flashrite programming
— Typical programming time of 16 seconds
s Latch-up protected to 100 mA from –1 V to
VCC + 1 V
s Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
s High noise immunity
GENERAL DESCRIPTION
The Am27C2048 is a 2 Mbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 128 K
words, operates from a single +5 V supply, has a static
standby mode, and features fast single address loca-
tion programming. The Am27C2048 is ideal for use in
16-bit microprocessor systems. The device is available
in windowed ceramic DIP packages, and plastic one
time programmable (OTP) PDIP and PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 16 seconds.
BLOCK DIAGRAM
OE#
CE#
PGM#
A0–A16
Address
Inputs
VCC
VSS
VPP
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
2,097,152
Bit Cell
Matrix
11407G-1
Publication# 11407 Rev: G Amendment/0
Issue Date: May 1998
1 page  
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed con-
tents, the device must be exposed to an ultraviolet light
source. A dosage of 15 W seconds/cm2 is required to
completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20
minutes. The device should be directly under and about
one inch from the source, and all filters should be re-
moved from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro-
cedure.
The device enters the programming mode when 12.75
V ± 0.25 V is applied to the VPP pin, and CE# and
PGM# are at VIL.
For programming, the data to be programmed is ap-
plied 16 bits in parallel to the data pins.
The flowchart in the Programming section (Section 5,
Figure 5-1) shows AMD’s Flashrite algorithm. The
Flashrite algorithm reduces programming time by using
a 100 µs programming pulse and by giving each address
only as many pulses to reliably program the data. After
each pulse is applied to a given address, the data in that
address is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process is repeated while se-
quencing through each address of the device. This part
of the algorithm is done at VCC = 6.25 V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at VCC = VPP =
5.25 V.
Please refer to Section 5 for additional programming in-
formation and specifications.
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#, all like in-
puts of the devices may be common. A TTL low-level
program pulse applied to one device’s CE# input with
VPP = 12.75 V ± 0.25 V and PGM# LOW will program
that particular device. A high-level CE# input inhibits
the other devices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# and CE#, at
VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro-
gramming the device.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the device outputs by tog-
gling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# con-
trols the power to the device and is typically used to se-
lect the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least tACC–tOE. Refer to the Switching
Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
s low memory power dissipation, and
s assurance that output bus contention will not occur.
CE# should be decoded and used as the primary de-
vice-selecting function, while OE# be made a common
connection to all devices in the array and connected to
Am27C2048
5
5 Page 
PHYSICAL DIMENSIONS*
CDV040—40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D
CENTER PLANE
INDEX AND
TERMINAL NO. 1
I.D. AREA
1
UV Lens
.565
.605
TOP VIEW
2.035
2.080
BASE PLANE
SEATING PLANE
.005 MIN
.045
.065
.014
.026
.015
.060
.100 BSC
SIDE VIEW
DATUM D
CENTER PLANE
.160
.220
.125
.200
.300 BSC
* For reference only. BSC is an ANSI standard for Basic Space Centering.
.700
MAX
94°
105°
.600
BSC
.008
.018
END VIEW
16-000038H-3
CDV040
DF11
3-30-95 ae
PD 040—40-Pin Plastic Dual In-Line Package (measured in inches)
2.040
2.080
40 21
.600
.625
Pin 1 I.D.
.045
.065
.140
.225
.530
.580
20
.005 MIN
.630
.700
0°
10°
.008
.015
SEATING PLANE
.120
.160
.090
.110
.015
.014 .060
.022
16-038-SC_AF
PD 040
DG76
2-28-95 ae
Am27C2048
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet Am27C2048-55JI5.PDF ] | |
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