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PDF AD9822 Data sheet ( Hoja de datos )
| Número de pieza | AD9822 | |
| Descripción | Complete 14-Bit CCD/CIS Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9822 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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Complete 14-Bit
CCD/CIS Signal Processor
AD9822
FEATURES
GENERAL DESCRIPTION
14-bit 15 MSPS ADC
No missing codes guaranteed
3-channel operation up to 15 MSPS
1-channel operation up to 12.5 MSPS
Correlated double sampling
1–6× programmable gain
±350 mV programmable offset
Input clamp circuitry
Internal voltage reference
Multiplexed byte-wide output (8 + 6 format)
3-wire serial digital interface
3 V/5 V digital I/O compatibility
28-Lead SOIC or SSOP
Low power CMOS: 385 mW (typ)
Power-down mode: <1 mW
APPLICATIONS
Flatbed document scanners
Film scanners
Digital color copiers
Multifunction peripherals
The AD9822 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture designed
to sample and condition the outputs of trilinear color CCD
arrays. Each channel consists of an input clamp, correlated double
sampler (CDS), offset DAC, and programmable gain amplifier
(PGA) multiplexed to a high performance 14-bit ADC.
The CDS amplifiers may be disabled for use with sensors such
as contact image sensors (CIS) and CMOS active pixel sensors,
which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal
registers are programmed through a 3-wire serial interface and
provide adjustment of the gain, offset, and operating mode.
The AD9822 operates from a single 5 V power supply,
consumes 385 mW of power typically, and is packaged in a
28-lead SOIC or SSOP.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
CML
CAPT
CAPB
AVDD
AVSS DRVDD DRVSS
VINR
VING
VINB
OFFSET
CDS
9-BIT
DAC
PGA
BAND GAP
REFERENCE
AD9822
CDS
PGA
3:1
MUX
14-BIT
ADC
14 14:8 8
MUX
9-BIT
DAC
CDS
INPUT
CLAMP
BIAS
9-BIT
DAC
PGA
6
9
CONFIGURATION
REGISTER
MUX
REGISTER
RED
GREEN
BLUE
RED
GREEN
BLUE
GAIN
REGISTERS
OFFSET
REGISTERS
DIGITAL
CONTROL
INTERFACE
CDSCLK1 CDSCLK2
ADCCLK
Figure 1.
OEB
DOUT
SCLK
SLOAD
SDATA
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9822
Parameter
POWER DISSIPATION
3-Channel Mode
3-Channel Mode @ 6 MHz
1-Channel Mode
1-Channel Mode @ 6 MHz
Min Typ
385
335
300
250
1 Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp.
Max
450
410
1V TYP
RESET TRANSIENT
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
2V p-p MAX INPUT SIGNAL RANGE
[ ]2 The PGA gain is approximately linear-in-dB and follows the equation: Gain =
5.7
where G is the register value. See Figure 15.
⎡ 63 − G ⎤
1 + 4.7 ⎢
⎣
63
⎥
⎦
Unit
mW
mW
mW
mW
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, CL = 10 pF, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
Symbol
VIH
VIL
IIH
IIL
CIN
VOH
VOL
IOH
IOL
Min Typ Max
2.0
0.8
10
10
10
4.5
0.1
50
50
Unit
V
V
µA
µA
pF
V
V
µA
µA
Rev. B | Page 4 of 20
5 Page 
AD9822
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
tADCLK
PIXEL N (R, G, B)
tAD
tC2
tC2ADF
tADC2
tC2ADR
PIXEL (N + 1)
tPRA
tADCLK
tOD
R (N– 2) G (N– 2) G (N– 2) B (N– 2) B (N– 2) R (N– 1) R (N– 1) G (N– 1) G (N– 1) B (N– 1) B (N– 1) R (N)
R (N)
G (N)
G (N)
HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW
BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE
Figure 5. 3-Channel SHA Mode Timing
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL (N – 4)
HIGH BYTE
PIXEL N
tAD
tC2
tPRB
tC2ADR
tADCLK
PIXEL (N – 4)
LOW BYTE
tC2ADF
tADCLK
tOD
PIXEL (N – 3)
HIGH BYTE
PIXEL (N – 3)
LOW BYTE
PIXEL (N – 2)
HIGH BYTE
Figure 6. 1-Channel SHA Mode Timing
PIXEL (N – 2)
LOW BYTE
Rev. B | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD9822.PDF ] | |
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