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PDF AD9826 Data sheet ( Hoja de datos )
| Número de pieza | AD9826 | |
| Descripción | Complete 16-Bit Imaging Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Complete 16-Bit Imaging
Signal Processor
AD9826
FEATURES
16-Bit 15 MSPS A/D Converter
3-Channel 16-Bit Operation up to 15 MSPS
1-Channel 16-Bit Operation up to 12.5 MSPS
2-Channel Mode for Mono Sensors with Odd/Even Outputs
Correlated Double Sampling
1~6؋ Programmable Gain
؎300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output
Optional Single Byte Output Mode
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
28-Lead SSOP Package
Low Power CMOS: 400 mW (Typ)
Power-Down Mode Available
APPLICATIONS
Flatbed Document Scanners
Digital Copier
Multifunction Peripherals
Infrared Imaging Applications
Machine Vision
PRODUCT DESCRIPTION
The AD9826 is a complete analog signal processor for imaging
applications. It features a 3-channel architecture designed to
sample and condition the outputs of trilinear color CCD arrays.
Each channel consists of an input clamp, Correlated Double
Sampler (CDS), offset DAC, and Programmable Gain Amplifier
(PGA), multiplexed to a high-performance 16-bit A/D converter.
The AD9826 can operate at speeds greater than 15 MSPS with
reduced performance.
The CDS amplifiers may be disabled for use with sensors that
do not require CDS, such as Contact Image Sensors (CIS),
CMOS active pixel sensors, and Focal Plane Arrays.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single byte output mode. The internal registers are programmed
through a 3-wire serial interface, and provide adjustment of
the gain, offset, and operating mode.
The AD9826 operates from a single 5 V power supply, typically
consumes 400 mW of power, and is packaged in a 28-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS CML
CAPT CAPB
AVDD AVSS
DRVDD DRVSS
VINR
VING
VINB
OFFSET
CDS
9-BIT
DAC
CDS
9-BIT
DAC
CDS
INPUT
CLAMP
BIAS
9-BIT
DAC
PGA
PGA
PGA
9
CDSCLK1 CDSCLK2
BANDGAP
REFERENCE
AD9826
3:1
MUX
16-BIT
16
16:8 8
ADC
MUX
CONFIGURATION
REGISTER
MUX
REGISTER
6
RED
GREEN
BLUE
RED
GREEN
BLUE
GAIN
REGISTERS
OFFSET
REGISTERS
ADCCLK
DIGITAL
CONTROL
INTERFACE
OEB
DOUT
SCLK
SLOAD
SDATA
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax:
© Analog Devices, Inc.,
1 page  
AD9826
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
To Min Max
Unit
VIN, CAPT, CAPB
Digital Inputs
AVDD
DRVDD
AVSS
Digital Outputs
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
AVSS
AVSS
AVSS
DRVSS
DRVSS
DRVSS
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.5 +6.5
V
–0.5 +6.5
V
–0.3 +0.3
V
–0.3 DRVDD + 0.3 V
150 °C
–65 +150
°C
300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 5.3 mm SSOP
θJA = 109°C/W
θJC = 39°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. B
5 Page 
AD9826
ANALOG
INPUTS
CDSCLK2
PIXEL n (R,G,B)
tAD
tC2
tC2AD
PIXEL (n+1)
tPRA
ADCCLK
tADCLK
tADC2
tC2ADR
OUTPUT
DATA
D<7:0>
tADCLK
tOD
R (n–2) G (n–2) G (n–2) B (n–2) B (n–2) R (n–1) R (n–1) G (n–1) G (n–1) B (n–1) B (n–1) R (n) R (n) G (n) G (n)
HIGH LOW
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
BYTE BYTE
Figure 5. 3-Channel SHA Mode Timing
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL n
tAD
tC2
tPRB
tC2ADR
tC2ADF
ttAADDCCLLKK
tADCLK
tOD
PIXEL (n–4)
PIXEL (n–4)
PIXEL (n–3)
PIXEL (n–3)
PIXEL (n–2)
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
NOTE
IN 1-CHANNEL SHA MODE,THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”
Figure 6. 1-Channel SHA Mode Timing
PIXEL (n–2)
LOW BYTE
–10–
REV. B
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD9826.PDF ] | |
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