PDF AD9830 Data sheet ( Hoja de datos )

Número de pieza	AD9830
Descripción	CMOS Complete DDS
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES +5 V Power Supply 50 MHz Speed On-Chip SINE Look-Up Table On-Chip 10-Bit DAC Parallel Loading Power-Down Option 72 dB SFDR 250 mW Power Consumption 48-Pin LQFP APPLICATIONS DDS Tuning Digital Demodulation DIRECT DIGITAL SYNTHESIZER, WAVEFORM GENERATOR AD9830 GENERAL DESCRIPTION This DDS device is a numerically controlled oscillator em- ploying a phase accumulator, a sine look-up table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 50 MHz are supported. Frequency accu- racy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the parallel micro- processor interface. A power-down pin allows external control of a power-down mode. The part is available in a 48-pin LQFP package. Similar DDS products can be found at http://www.analog.com/DDS. FUNCTIONAL BLOCK DIAGRAM MCLK FSELECT FREQ0 REG FREQ1 REG DVDD DGND AVDD AGND REFOUT FS ADJUST REFIN ON-BOARD REFERENCE FULL SCALE CONTROL MUX PHASE ACCUMULATOR (32-BIT) 12 Σ SIN ROM 10-BIT DAC COMP IOUT IOUT PHASE0 REG PHASE1 REG PHASE2 REG PHASE3 REG MUX PARALLEL REGISTER TRANSFER CONTROL MPU INTERFACE D0 D15 WR A0 A1 A2 AD9830 SLEEP RESET PSEL0 PSEL1 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 2011 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 781-461-3113 1 page AD9830 TIMING CHARACTERISTICS (VDD = +5 V ؎ 5%; AGND = DGND = 0 V, unless otherwise noted) Parameter Limit at TMIN to TMAX (A Version) Units Test Conditions/Comments t1 20 t2 8 t3 8 t41 8 t4A1 8 t5 8 t6 t1 t7 5 t8 3 t91 8 t9A1 8 t10 t1 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min NOTES 1See Pin Description section. Guaranteed by design, but not production tested. MCLK Period MCLK High Duration MCLK Low Duration WR Rising Edge Before MCLK Rising Edge WR Rising Edge After MCLK Rising Edge WR Pulse Width Duration Between Consecutive WR Pulses Data/Address Setup Time Data/Address Hold Time FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge RESET Pulse Duration MCLK t1 t2 t3 t4 t5 WR t4A t6 Figure 2. WR–MCLK Relationship t6 t5 WR A0, A1, A2 DATA t8 t7 VALID DATA Figure 3. Writing to a Phase/Frequency Register VALID DATA MCLK FSELECT PSEL0, PSEL1 VALID DATA t9 VALID DATA t9A VALID DATA REV. B RESET t10 Figure 4. Control Timing –3– 5 Page 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 START 0Hz RBW 1kHz VBW 3kHz STOP 25MHz ST 50 SEC Figure 17. fMCLK = 50 MHz, fOUT = 16.5 MHz, Frequency Word = 547AE148 AD9830 Register Size FREQ0 REG 32 Bits FREQ1 REG 32 Bits PHASE0 REG 12 Bits PHASE1 REG 12 Bits PHASE2 REG 12 Bits PHASE3 REG 12 Bits Description Frequency Register 0. This defines the output frequency, when FSELECT = 0, as a fraction of the MCLK frequency. Frequency Register 1. This de- fines the output frequency, when FSELECT = 1, as a fraction of the MCLK frequency. Phase Offset Register 0. When PSEL0 = PSEL1 = 0, the contents of this register are added to the out- put of the phase accumulator. Phase Offset Register 1. When PSEL0 = 1 and PSEL1 = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 2. When PSEL0 = 0 and PSEL1 = 1, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 3. When PSEL0 = PSEL1 = 1, the contents of this register are added to the out- put of the phase accumulator. Figure 18. AD9830 Control Registers A2 A1 A0 Destination Register 0 0 0 FREQ0 REG 16 LSBs 0 0 1 FREQ0 REG 16 MSBs 0 1 0 FREQ1 REG 16 LSBs 0 1 1 FREQ1 REG 16 MSBs 1 0 0 PHASE0 REG 1 0 1 PHASE1 REG 1 1 0 PHASE2 REG 1 1 1 PHASE3 REG Figure 19. Addressing the Control Registers D15 MSB Figure 20. Frequency Register Bits D0 LSB D15 D14 D13 D12 D11 X X X X MSB X = Don't Care Figure 21. Phase Register Bits D0 LSB REV. B –9– 11 Page

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