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PDF AD9835 Data sheet ( Hoja de datos )
| Número de pieza | AD9835 | |
| Descripción | 50 MHz CMOS Complete DDS | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
50 MHz Direct Digital Synthesizer,
Waveform Generator
AD9835
FEATURES
5 V power supply
50 MHz speed
On-chip COS lookup table
On-chip, 10-bit DAC
Serial loading
Power-down option
Temperature range: −40°C to +85°C
200 mW power consumption
16-Lead TSSOP
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect
detection
Test and medical equipment
GENERAL DESCRIPTION
The AD9835 is a numerically-controlled oscillator employing
a phase accumulator, a COS lookup table, and a 10-bit digital-
to-analog converter integrated on a single CMOS chip. Modu-
lation capabilities are provided for phase modulation and
frequency modulation.
Clock rates of up to 50 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is effected
by loading registers through the serial interface. A power-down
bit allows the user to power down the AD9835 when it is not in
use; the power consumption reduces to 1.75 mW.
This part is available in a 16-lead TSSOP package.
Similar DDS products can be found at
http://www.analog.com/DDS.
MCLK
FSELECT
FUNCTIONAL BLOCK DIAGRAM
DVDD DGND
AVDD AGND
REFOUT FS ADJUST REFIN
FSELECT
BIT
SELSRC
SYNC
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
FREQ0 REG
FREQ1 REG
PHASE
ACCUMULATOR
(32 BIT)
12 COS
ROM
10-BIT DAC
COMP
IOUT
SYNC
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
16-BIT DATA REGISTER
MUX
8 MSBs
8 LSBs DEFER REGISTER
AD9835
SYNC
SYNC
SELSRC
MUX
MUX
DECODE LOGIC
SERIAL REGISTER
CONTROL REGISTER
FSELECT/PSEL REGISTER
PSEL0
BIT
PSEL1
BIT
FSYNC SCLK SDATA
Figure 1.
PSEL0 PSEL1
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1998–2011 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
AD9835
SPECIFICATIONS
VDD = +5 V ± 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; RSET = 3.9 kΩ; RLOAD = 300 Ω for IOUT, unless otherwise
noted. Also, see Figure 2.
Table 1.
Parameter1
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate (fMAX)
IOUT Full Scale
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS2
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range (SFDR)3
Narrow Band (±50 kHz)
Wide Band (±2 MHz)
Clock Feedthrough
Wake-Up Time
Power-Down Option
VOLTAGE REFERENCE
Internal Reference @ +25° C
TMIN to TMAX
REFIN Input Impedance
Reference TC
REFOUT Output Impedance
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
POWER SUPPLIES
AVDD
DVDD
IAA
IDD
IAA + IDD4
Low Power Sleep Mode
Min Typ
50
4
±1
±0.5
50
−72
−50
−60
1
1.131
1.21
10
100
300
DVDD − 0.9
4.75
4.75
2.5 +
0.33/MHz
Max
10
4.75
1.35
−52
1.29
0.9
10
10
5.25
5.25
5
40
0.35
Units
Bits
MSPS
mA
mA
V
LSB
LSB
Test Conditions/Comments
dB fMCLK = 50 MHz, fOUT = 1 MHz
dBc fMCLK = 50 MHz, fOUT = 1 MHz
fMCLK = 6.25 MHz, fOUT = 2.11 MHz
dBc
dBc
dBc
ms
Yes
V
V
MΩ
ppm/°C
Ω
V
V
μA
pF
V min/V max
V min/V max
mA max
mA typ
fMCLK = 50 MHz
mA max
mA max
1 Operating temperature range is as follows: B Version: −40°C to +85°C.
2 100% production tested.
3 fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.
4 Measured with the digital inputs static and equal to 0 V or DVDD. The AD9835 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive
loads, but the magnitude of the analog output will be attenuated. See Figure 7.
Rev. A | Page 3 of 28
5 Page 
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
AVDD = DVDD = +5V
–2
–4
CL = 82pF
–6
–8
CL = 150pF
–10
CL = 100pF
–12
0 2 4 6 8 10 12 14 16
OUTPUT FREQUENCY (MHz)
Figure 7. Signal Attenuation vs. Output Frequency for Various Capacitive
Loads (RL = 300 Ω)
30
TA = +25°C
AVDD = DVDD = +5V
25
20
15
10
5
0
10 20 30 40 50
MCLK FREQUENCY (MHz)
Figure 8. Typical Current Consumption vs. MCLK Frequency
–64 fOUT/fMCLK = 1/3
AVDD = DVDD = +5V
–66
–68
–70
–72
–74
–76
10 20 30 40
MCLK FREQUENCY (MHz)
Figure 9. Narrow-Band SFDR vs. MCLK Frequency
50
AD9835
0
fOUT/fMCLK = 1/3
AVDD = DVDD = +5V
–10
–20
–30
–40
–50
–60
10
20 30 40
MCLK FREQUENCY (MHz)
Figure 10. Wideband SFDR vs. MCLK Frequency
50
–20
AVDD = DVDD = +5V
–30
–40
–50 50MHz
30MHz
–60
–70 10MHz
–80
0.044
0.084
0.124
0.164 0.204 0.244
fOUT/fMCLK
0.284
0.324
0.463
Figure 11. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies
56
fOUT/fMCLK = 1/3
AVDD = DVDD = +5V
55
54
53
52
51
50
10 20 30 40
MCLK FREQUENCY (MHz)
Figure 12. SNR vs. MCLK Frequency
50
Rev. A | Page 9 of 28
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9835.PDF ] | |
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