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PDF AD9840A Data sheet ( Hoja de datos )
| Número de pieza | AD9840A | |
| Descripción | Complete 10-Bit 40 MSPS CCD Signal Processor | |
| Fabricantes | Analog Devices | |
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FEATURES
40 MSPS Correlated Double Sampler (CDS)
4 dB ؎ 6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 40 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 155 mW @ 3.0 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Video Camcorders
Digital Still Cameras
Industrial Imaging
Complete 10-Bit 40 MSPS
CCD Signal Processor
AD9840A
PRODUCT DESCRIPTION
The AD9840A is a complete analog signal processor for CCD
applications. It features a 40 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9840A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
The AD9840A operates from a 3 V power supply, typically
dissipates 155 mW, and is packaged in a 48-lead LQFP.
CCDIN
CLPDM
AUX1IN
AUX2IN
PBLK
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
CLPOB
4dB؎6dB
CDS
CLP
2:1
MUX
BUF
CLP
AD9840A
2dB TO 36dB
2:1
MUX
VGA
CLP
10-BIT
ADC
10
10
6
INTERNAL
REGISTERS
OFFSET
DAC
8
BANDGAP
REFERENCE
INTERNAL
BIAS
DIGITAL
INTERFACE
INTERNAL
TIMING
DRVDD
DRVSS
DOUT
VRT
VRB
CML
DVDD
DVSS
SL SCK SDATA
SHP SHD DATACLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD9840A
TIMING SPECIFICATIONS (CL = 20 pF, fSAMP = 40 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
Parameter
Symbol
Min
Typ Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK Hi/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
tCP
tADC
tSHP
tSHD
tCDM
tCOB
tS1
tS2
tID
tINH
tOD
tH
25
10
5
5
4
2
0
10
10
7.0
12.5
6
6
10
20
6
12.5
3.0
14.5 16
7.6
9
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
ns
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
NOTES
1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS
Parameter
With
Respect
To Min Max
Unit
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
(10 sec)
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
150 °C
300 °C
ORDERING GUIDE
Model
Temperature
Range
AD9840AJST –20°C to +85°C
Package
Description
Thin Plastic
Quad Flatpack
(LQFP)
Package
Option
ST-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 92°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9840A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
5 Page 
AD9840A
DC RESTORE
6
CDS GAIN
REGISTER
0.1F CCDIN
–2dB TO +10dB
CDS
INPUT OFFSET
CLAMP
CLPDM
2dB TO 36dB
VGA
INTERNAL
VREF
2V FULL SCALE
10-BIT
ADC
10
10
VGA GAIN
REGISTER
8-BIT
DAC
OPTICAL BLACK
CLAMP
DIGITAL
FILTERING
0 TO 64 LSB
8
DOUT
CLPOB
CLAMP LEVEL
REGISTER
Figure 11. CCD-Mode Block Diagram
CIRCUIT DESCRIPTION AND OPERATION
The AD9840A signal processing chain is shown in Figure 11.
Each processing step is essential in achieving a high-quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a
dc-restore circuit is used with an external 0.1 µF series-coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V, to be compatible with the 3 V single supply of
the AD9840A.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal respectively. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (tID) of 3 ns is caused by internal
propagation delays.
The CDS stage has a default gain of 4 dB, but uses a unique
architecture that allows the CDS gain to be varied. Using the
CDS Gain Register, the gain-of is programmable from –2 dB to
+10 dB in 64 steps, using two’s complement coding. The CDS
Gain curve is shown in Figure 12. To change the gain of the
CDS using the CDS Gain Register, the Control Register bit D3
must be set high (CDS Gain Enabled). The default gain setting
when bit Control Register Bit D3 is low (CDS Gain Disabled) is
4 dB. See Tables V and VI for more details.
A CDS gain of 4 dB provides some front-end signal gain and
improves the overall signal-to-noise ratio. This gain setting
works very well in most applications, and the CCD-Mode
Specifications use this default gain setting. However, the CDS
gain may be varied to optimize the AD9840A operation in a
particular application. Increased CDS gain can be useful with
low output level CCDs, while decreased CDS gain allows the
AD9840A to accept CCD signal swings greater than 1 V p-p.
Table VII summarizes some example CDS gain settings for
different maximum signal swings. The CDS Gain Register may
also be used “on the fly” to provide a +6 dB boost or –6 dB
attenuation when setting exposure levels. It is best to keep the
CDS output level from exceeding 1.5 V–1.6 V.
Table VII. Example CDS Gain Settings
Max Input Signal
250 mV p-p
500 mV p-p
800 mV p-p
1 V p-p
1.25 V p-p
1.5 V p-p
Recommended
Gain Range
8 dB to 10 dB
6 dB to 8 dB
4 dB to 6 dB
2 dB to 4 dB
0 dB to 2 dB
–2 dB to 0 dB
Register Code Range
21 to 31
10 to 21
63 to 10
53 to 63
42 to 53
32 to 42
10
8
6
4
2
0
-2
32
40
(100000)
48 56 0 8 16
CDS GAIN REGISTER CODE
24 31
(011111)
Figure 12. CDS Gain Curve
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded
black reference pixels. Unlike some AFE architectures, the
AD9840A removes this offset in the input stage to minimize the
effect of a gain change on the system black level, usually called the
“gain step.” Another advantage of removing this offset at the
input stage is to maximize system headroom. Some area CCDs
have large black level offset voltages, which, if not corrected at
the input stage, can significantly reduce the available headroom
in the internal circuitry when higher VGA gain settings are used.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
REV. 0
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet AD9840A.PDF ] | |
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