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AD9842A 데이터시트 PDF




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부품번호 AD9842A 기능
기능 Complete 20 MSPS CCD Signal Processors
제조업체 Analog Devices
로고 Analog Devices 로고


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AD9842A 데이터시트, 핀배열, 회로
a
FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB ؎ 6 dB 6-Bit Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit (9841) or 12-Bit (9842) 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Complete 20 MSPS
CCD Signal Processors
AD9841A/AD9842A
PRODUCT DESCRIPTION
The AD9841A and AD9842A are complete analog signal proces-
sors for CCD applications. Both products feature a 20 MHz
single-channel architecture designed to sample and condition
the outputs of interlaced and progressive scan area CCD arrays.
The AD9841A/AD9842A’s signal chain consists of an input
clamp, correlated double sampler (CDS), Pixel Gain Amplifier
(PxGA), digitally controlled variable gain amplifier (VGA),
black level clamp, and A/D converter. The AD9841A offers 10-bit
ADC resolution, while the AD9842A contains a true 12-bit
ADC. Additional input modes are provided for processing analog
video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
The AD9841A and AD9842A operate from a single 3 V power
supply, typically dissipate 78 mW, and are packaged in a 48-
lead LQFP.
CCDIN
CLPDM
AUX1IN
AUX2IN
FUNCTIONAL BLOCK DIAGRAM
PBLK
AVDD
AVSS
HD
VD
CLPOB
4dB ؎ 6dB
CDS
PxGA
CLP
6
2:1
MUX
BUF
CLP
AD9841A/AD9842A
COLOR
STEERING
2:1
MUX
2dB–36dB
VGA
CLP
ADC
10/12
DRVDD
DRVSS
DOUT
OFFSET
10 DAC
CONTROL
REGISTERS
DIGITAL
INTERFACE
8
BANDGAP
REFERENCE
INTERNAL
BIAS
INTERNAL
TIMING
VRT
VRB
CML
DVDD
DVSS
SL SCK SDATA
SHP SHD DATACLK
PxGA is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001




AD9842A pdf, 반도체, 판매, 대치품
AD9841A/AD9842A–SPECIFICATIONS
AD9842A CCD-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless
otherwise noted)
Parameter
Min Typ Max
Unit
Notes
POWER CONSUMPTION
78 mW See TPC 1 for Power Curves
MAXIMUM CLOCK RATE
20
MHz
CDS
Gain
Allowable CCD Reset Transient1
Max Input Range Before Saturation1
Max CCD Black Pixel Amplitude1
0
500
1.0
200
dB
mV
V p-p
mV
See Input Waveform in Footnote 1
PxGA Gain at 4 dB
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range (Two’s Complement Coding)
Min Gain (PxGA Gain Code 32)
Max Gain (PxGA Gain Code 31)
1.0
1.6
64
Guaranteed
–2
10
V p-p
V p-p
Steps
dB
dB
See Figure 28 for PxGA Gain Curve
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Gain Code 91)
Max Gain (VGA Gain Code 1023)
1.6
2.0
1024
Guaranteed
2
36
V p-p
V p-p
Steps
dB
dB
See Figure 29 for VGA Gain Curve
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
256 Steps
Measured at ADC Output
0 LSB
255 LSB
SYSTEM PERFORMANCE
Gain Accuracy, (VGA Code 91 to 1023)2
PxGA Gain Accuracy
Min Gain (PxGA Register Code 32)
Max Gain (PxGA Code 31)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
–0.5
–1
11
0
12
0.1
0.6
40
+0.5
+1
13
Specifications Include Entire Signal Chain
Use Equations on Page 19 to Calculate Gain
dB
dB
%
LSB rms
dB
VGA Gain Fixed at 2 dB (Code 91)
VGA Gain Fixed at 2 dB (Code 91)
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with step change on supply
POWER-UP RECOVERY TIME
Fast Recovery Mode
Reference Standby Mode
Total Shutdown Mode
Power-Off Condition
Normal Clock Signals Applied
0.1 ms
1 ms
3 ms
15 ms
NOTES
1Input Signal Characteristics defined as follows:
500mV TYP
RESET TRANSIENT
200mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
2PxGA gain fixed at 4 dB.
Specifications subject to change without notice.
–4– REV. 0

4페이지










AD9842A 전자부품, 판매, 대치품
PIN CONFIGURATIONS
AD9841A/AD9842A
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
NC 2
(LSB) D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
D8 11
(MSB) D9 12
PIN 1
IDENTIFIER
AD9841A
TOP VIEW
(Not to Scale)
36 AUX1IN
35 AVSS
34 AUX2IN
33 AVDD2
32 BYP4
31 NC
30 CCDIN
29 BYP2
28 BYP1
27 AVDD1
26 AVSS
25 AVSS
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
D8 9
D9 10
D10 11
(MSB) D11 12
PIN 1
IDENTIFIER
AD9842A
TOP VIEW
(Not to Scale)
36 AUX1IN
35 AVSS
34 AUX2IN
33 AVDD2
32 BYP4
31 NC
30 CCDIN
29 BYP2
28 BYP1
27 AVDD1
26 AVSS
25 AVSS
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin Number
Name
Type
Description
1, 2
3–12
1–12
13
14
15, 41
16
17
18
19
20
21
22
23
24
25, 26, 35
27
28
29
30
31
32
33
34
36
37
38
39
40
42
43
44
45
46
47
48
NC
D0–D9
D0–D11
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
HD
PBLK
CLPOB
SHP
SHD
CLPDM
VD
AVSS
AVDD1
BYP1
BYP2
CCDIN
NC
BYP4
AVDD2
AUX2IN
AUX1IN
CML
VRT
VRB
DVDD2
THREE-STATE
NC
STBY
NC
SL
SDATA
SCK
NC
DO
DO
P
P
P
DI
P
DI
DI
DI
DI
DI
DI
DI
P
P
AO
AO
AI
NC
AO
P
AI
AI
AO
AO
AO
P
DI
NC
DI
NC
DI
DI
DI
Internally Not Connected (AD9841A ONLY)
Digital Data Outputs (AD9841A ONLY)
Digital Data Outputs (AD9842A ONLY)
Digital Output Driver Supply
Digital Output Driver Ground
Digital Ground
Digital Data Output Latch Clock
Digital Supply
Horizontal Drive. Used with VD for Color Steering Control
Preblanking Clock Input
Black Level Clamp Clock Input
CDS Sampling Clock for CCD’s Reference Level
CDS Sampling Clock for CCD’s Data Level
Input Clamp Clock Input
Vertical Drive. Used with HD for Color Steering Control
Analog Ground
Analog Supply
Internal Bias Level Decoupling
Internal Bias Level Decoupling
Analog Input for CCD Signal
Internally Not Connected
Internal Bias Level Decoupling
Analog Supply
Analog Input
Analog Input
Internal Bias Level Decoupling
A/D Converter Top Reference Voltage Decoupling
A/D Converter Bottom Reference Voltage Decoupling
Digital Supply
Digital Output Disable. Active High
May be tied high or low. Do not leave floating.
Standby Mode, Active High. Same as Serial Interface
Internally Not Connected. May be Tied High or Low
Serial Digital Interface Load Pulse
Serial Digital Interface Data
Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–7–

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AD9842A

Complete 20 MSPS CCD Signal Processors

Analog Devices
Analog Devices

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