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부품번호 | AD9846A 기능 |
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기능 | Complete 10-Bit 30 MSPS CCD Signal Processor | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 24 페이지수
a
FEATURES
30 MSPS Correlated Double Sampler (CDS)
4 dB ؎ 6 dB 6-Bit Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 30 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 100 mW @ 2.7 V
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
Complete 10-Bit 30 MSPS
CCD Signal Processor
AD9846A
PRODUCT DESCRIPTION
The AD9846A is a complete analog signal processor for CCD
applications. It features a 30 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9846A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
Pixel Gain Amplifier (PxGA), digitally controlled variable gain
amplifier (VGA), black level clamp, and a 10-bit A/D con-
verter. Additional input modes are provided for processing
analog video signals.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input configuration, and
power-down modes.
The AD9846A operates from a single 3 V power supply, typi-
cally dissipates 117 mW, and is packaged in a 48-lead LQFP.
CCDIN
CLPDM
AUX1IN
AUX2IN
PBLK
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
HD
VD
CLPOB
4dB؎6 dB
CDS
PxGA
CLP
6
2:1
MUX
BUF
CLP
AD9846A
COLOR
STEERING
2:1
MUX
2dB~36dB
VGA
OFFSET
10 DAC
CONTROL
REGISTERS
DIGITAL
INTERFACE
8
CLP
DRVDD
DRVSS
ADC
DOUT
10
BANDGAP
REFERENCE
VRT
VRB
INTERNAL
BIAS
CML
INTERNAL
TIMING
DVDD
DVSS
SL SCK SDATA
SHP SHD DATACLK
PxGA is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9846A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
82 mW
MAXIMUM CLOCK RATE
30
MHz
INPUT BUFFER
Gain
Max Input Range
0
1.0
dB
V p-p
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
Max Gain
2.0
1023
0
36
V p-p
Steps
dB
dB
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
86 mW
MAXIMUM CLOCK RATE
30
MHz
INPUT BUFFER
(Same as AUX1-MODE)
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
Max Gain
2.0
512
0
18
V p-p
Steps
dB
dB
ACTIVE CLAMP
Clamp Level Resolution
Clamp Level (Measured at ADC Output)
Min Clamp Level
Max Clamp Level
256
0
63.75
Steps
LSB
LSB
Specifications subject to change without notice.
–4– REV. 0
4페이지 AD9846A
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9846A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2N codes) when N is the bit resolution of the
ADC. For the AD9846A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9846A’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9846A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
DVDD
330⍀
AVDD1
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DRVDD
DATA
THREE-
STATE
DOUT
RNW
REV. 0
DVSS
DRVSS
Figure 2. Data Outputs—D0–D9
–7–
AVSS
AVSS
Figure 3. CCDIN (Pin 30)
DVDD
DATA IN
DATA OUT
DVDD
330⍀
DVSS
DVSS
DVSS
Figure 4. SDATA (Pin 47)
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부품번호 | 상세설명 및 기능 | 제조사 |
AD9846A | Complete 10-Bit 30 MSPS CCD Signal Processor | Analog Devices |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |