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PDF AD9849 Data sheet ( Hoja de datos )
| Número de pieza | AD9849 | |
| Descripción | CCD Signal Processors | |
| Fabricantes | Analog Devices | |
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FEATURES
AD9848: 10-Bit, 20 MHz Version
AD9849: 12-Bit, 30 MHz Version
Correlated Double Sampler (CDS)
–2 dB to +10 dB Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 20 MHz A/D Converter (AD9848)
12-Bit 30 MHz A/D Converter (AD9849)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing™ Core with 1 ns Resolution @ 20 MSPS
On-Chip 3 V Horizontal and RG Drivers (AD9848)
On-Chip 5 V Horizontal and RG Drivers (AD9849)
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
CCD Signal Processors with
Integrated Timing Driver
AD9848/AD9849
PRODUCT DESCRIPTION
The AD9848 and AD9849 are highly integrated CCD signal pro-
cessors for digital still camera applications. Both include a complete
analog front end with A/D conversion, combined with a program-
mable timing driver. The Precision Timing core allows adjustment
of high speed clocks with approximately 1 ns resolution.
The AD9848 is specified at pixel rates of 20 MHz, and the
AD9849 is specified at 30 MHz. The analog front end includes
black level clamping, CDS, PxGA, VGA, and a 10-bit or 12-bit A/D
converter. The timing driver provides the high speed CCD clock
drivers for RG and H1–H4. Operation is programmed using a
3-wire serial interface.
Packaged in a space saving 48-lead LQFP, the AD9848 and
AD9849 are specified over an operating temperature range of
–20°C to +85°C.
CCDIN
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
CDS
4؎6dB
PxGA
2dB TO 36dB
VGA
VREF
ADC
10 OR 12
DOUT
CLAMP
RG
HORIZONTAL
4 DRIVERS
H1–H4
AD9848/AD9849
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
HD VD
CLAMP
CLPOB
CLPDM
PBLK
CLI
INTERNAL
REGISTERS
SL SCK SDATA
PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc.
1 page  
AD9848/AD9849
AD9849–ANALOG SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 30 MHz, unless otherwise noted.)
Parameter
Min Typ
Max Unit Notes
CDS
Gain
0
Allowable CCD Reset Transient*
500
Max Input Range Before Saturation* 1.0
Max CCD Black Pixel Amplitude*
150
dB
mV
V p-p
mV
See Input Waveform in Note
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (32)
Med Gain (0)
Max Gain (31)
1.0
1.6
64
Guaranteed
–2
4
10
V p-p
V p-p
Steps
dB
dB Medium Gain (4 dB) Is Default Setting
dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (91)
Max Gain (1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level (0)
Max Clamp Level (255)
1.6
2.0
1024
Guaranteed
2
36
256
0
255
V p-p
V p-p
Steps
dB
dB
Steps
LSB
LSB
Measured at ADC Output
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
12 Bits
± 0.5 ± 1.0 LSB
Guaranteed
2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (91)
5
Max Gain (1023)
38
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
2.0
1.0
6
39.5
0.2
0.6
40
V
V
Specifications Include Entire Signal Chain
Gain Includes 4 dB Default PxGA Gain
7 dB
41 dB
% 12 dB Gain Applied
LSB rms AC Grounded Input, 6 dB Gain Applied
dB Measured with Step Change on Supply
*Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
150mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
Specifications subject to change without notice.
REV. A
–5–
5 Page 
SYSTEM OVERVIEW
CCD
V-DRIVER
H1–H4, RG
CCDIN
V1–V4, VSG1–VSG8, SUBCK
DOUT
AD9848/AD9849
INTEGRATED
AFE+TD
DIGITAL IMAGE
PROCESSING
HD, VD
ASIC
SERIAL
INTERFACE
CLI
Figure 1a. Typical Application (Internal Mode)
AD9848/AD9849
CCD
V-DRIVER
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
CCDIN
AD9848/AD9849
INTEGRATED
AFE+TD
DOUT
CLPOB
CLPDM
PBLK
HBLK
HD, VD
DIGITAL IMAGE
PROCESSING
ASIC
CLI
SERIAL
INTERFACE
Figure 1b. Typical Application (External Mode)
Figures 1a and 1b show the typical system application diagrams
for the AD9848/AD9849. The CCD output is processed by the
AD9848/AD9849’s AFE circuitry, which consists of a CDS,
PxGA, VGA, black level clamp, and A/D converter. The
digitized pixel information is sent to the digital image
processor chip, where all post-processing and compression
occurs. To operate the CCD, CCD timing parameters are
programmed into the AD9848/AD9849 from the image
processor, through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor, the
AD9848/AD9849 generates the high speed CCD clocks and all
internal AFE clocks. All AD9848/AD9849 clocks are
synchronized with VD and HD.
Figure 1a shows the AD9848/AD9849 used in Internal Mode, in
which all the horizontal pulses (CLPOB, CLPDM, PBLK,
and HBLK) are programmed and generated internally. Figure 1b
shows the AD9848/AD9849 operating in External Mode, in
which the horizontal pulses are supplied externally by the
image processor.
The H-drivers for H1–H4 and RG are included in the AD9848/
AD9849, allowing these clocks to be directly connected to the
CCD. H-drive voltage of 5 V is supported in the AD9849.
Figure 2 shows the horizontal and vertical counter dimensions
for the AD9848/AD9849. All internal horizontal clocking is
programmed using these dimensions to specify line and
pixel locations.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
Figure 2. Vertical and Horizontal Counters
REV. A
–11–
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| PDF Descargar | [ Datasheet AD9849.PDF ] | |
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