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부품번호 AD9862 기능
기능 Mixed-Signal Front-End (MxFE) Processor for Broadband Communications
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AD9862 데이터시트, 핀배열, 회로
a Mixed-Signal Front-End (MxFE) Processor
for Broadband Communications
AD9860/AD9862*
FEATURES
Mixed-Signal Front-End Processor with Dual Converter
Receive and Dual Converter Transmit Signal Paths
Receive Signal Path Includes:
Two 10-/12-Bit, 64 MSPS Sampling A/D Converters
with Internal or External Independent References,
Input Buffers, Programmable Gain Amplifiers,
Low-Pass Decimation Filters, and a Digital Hilbert Filter
Transmit Signal Path Includes:
Two 12-/14-Bit, 128 MSPS D/A Converters with
Programmable Full-Scale Output Current, Channel
Independent Fine Gain and Offset Control, Digital
Hilbert and Interpolation Filters, and Digitally Tunable
Real or Complex Up-Converters
Delay-Locked Loop Clock Multiplier and Integrated
Timing Generation Circuitry Allow for Single Crystal
or Clock Operation
Programmable Output Clocks, Serial Programmable
Interface, Programmable Sigma-Delta, Three Auxiliary
DAC Outputs and Two Auxiliary ADCs with Dual
Multiplexed Inputs
APPLICATIONS
Broadband Wireless Systems
Fixed Wireless, WLAN, MMDS, LMDS
Broadband Wireline Systems
Cable Modems, VDSL, PowerPlug
Digital Communications
Set-Top Boxes, Data Modems
GENERAL DESCRIPTION
The AD9860 and AD9862 (AD9860/AD9862) are versatile
integrated mixed-signal front-ends (MxFE) that are optimized
for broadband communication markets. The AD9860/AD9862
are cost effective, mixed signal solutions for wireless or wireline
standards based or proprietary broadband modem systems where
dynamic performance, power dissipation, cost, and size are all
critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;
the AD9862 has 12-bit ADCs and 14-bit DACs.
The AD9860/AD9862 receive path (Rx) consists of two channels
that each include a high performance, 10-/12-bit, 64 MSPS analog-
to-digital converter (ADC), input buffer, Programmable Gain
Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The
Rx can be used to receive real, diversity, or I/Q data at baseband or
low IF. The input buffers provide a constant input impedance for
both channels to ease impedance matching with external com-
ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain
*Protected by U.S.Patent No. 5,969,657; other patents pending.
MxFE is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VIN+B
VIN–B
SIGDELT
AUX_DAC_A
AUX_DAC_B
AUX_DAC_C
AUX_ADC_A1
AUX_ADC_A2
AUX_ADC_B1
AUX_ADC_B2
IOUT+A
IOUT–A
IOUT+B
IOUT–B
1x PGA
ADC
BYPASSABLE LOW-PASS HILBERT
DECIMATION FILTER
FILTER
1x PGA
ADC
LOGIC LOW
-
AD9860/AD9862
AUX DAC
SPI REGISTERS
AUX DAC
AUX DAC
AUX ADC
Rx PATH
TIMING
Tx PATH
TIMING
CLOCK
DISTRIBUTION
BLOCK
DLL
1؋, 2؋, 4؋
PGA
PGA
AUX ADC
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
DAC
DAC
FS/4
FS/8
BYPASSABLE
LOW-PASS
INTERPOLATION
FILTER
NCO
HILBERT
FILTER
RxA DATA
[0:11]
RxB DATA
[0:11]
SPI
INTERFACE
OSC1
OSC2
CLKOUT1
CLKOUT2
Tx DATA
[0:13]
range for both channels. The output data bus can be multi-
plexed to accommodate a variety of interface types.
The AD9860/AD9862 transmit path (Tx) consists of two chan-
nels that contain high performance, 12-/14-bit, 128 MSPS
digital-to-analog converters (DAC), programmable gain amplifiers
(TxPGA), interpolation filters, a Hilbert filter, and digital mixers
for complex or real signal frequency modulation. The Tx latch
and demultiplexer circuitry can process real or I/Q data. Interpo-
lation rates of 2ϫ and 4ϫ are available to ease requirements on
an external reconstruction filter. For single channel systems, the
digital Hilbert filter can be used with an external quadrature
modulator to create an image rejection architecture. The two
12-/14-bit, high performance DACs produce an output signal
that can be scaled over a 20 dB range by the TxPGA.
A programmable delay-locked loop (DLL) clock multiplier and
integrated timing circuits enable the use of a single external
reference clock or an external crystal to generate clocking for all
internal blocks and also provides two external clock outputs.
Additional features include a programmable sigma-delta output,
four auxiliary ADC inputs and three auxiliary DAC outputs.
Device programmability is facilitated by a serial port interface
(SPI) combined with a register bank. The AD9860/AD9862 is
available in a space saving 128-lead LQFP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002




AD9862 pdf, 반도체, 판매, 대치품
AD9860/AD9862
PARAMETERS (continued)
Temp
POWER SUPPLY (continued)
Rx Path (fADC = 64 MSPS)
Processing Blocks Disabled
Decimation Filter Enabled
Hilbert Filter Enabled
Hilbert and Decimation Filter Enabled
25ºC
25ºC
25ºC
25ºC
NOTES
1% fDATA refers to the input data rate of the digital block.
2Interpolation filter stop band is defined by image suppression of 50 dB or greater.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Test
Level
III
III
III
III
AD9860/AD9862
Min Typ Max
9
15
16
18.5
(20 pF Load)
Minimum Reset Pulsewidth Low (tRL)
Digital Output Rise/Fall Time
DLL Output Clock
DLL Output Duty Cycle
Tx/RxInterface (See Figures 11 and 12)
TxSYNC/TxIQ Setup Time (tTx1, tTx3)
TxSYNC/TxIQ Hold Time (tTx2, tTx4)
RxSYNC/RxIQ/IF to Valid Time(tRx1, tRx3)
RxSYNC/RxIQ/IF Hold Time (tRx2, tRx4)
Serial Control Bus (See Figures 1 and 2)
Maximum SCLK Frequency (fSCLK)
Minimum Clock Pulsewidth High (tHI)
Minimum Clock Pulsewidth Low (tLOW)
Maximum Clock Rise/Fall Time
Minimum Data/SEN Setup Time (tS)
Minimum SEN/Data Hold Time (tH)
Minimum Data/SCLK Setup Time (tDS)
Minimum Data Hold Time (tDH)
Output Data Valid/SCLK Time (tDV)
AUXILARY ADC
Conversion Rate
Input Range
Resolution
AUXILARY DAC
Settling Time
Output Range
Resolution
ADC TIMING
Latency (All Digital Processing Blocks Disabled)
DAC Timing
Latency (All Digital Processing Blocks Disabled)
Latency (2ϫ Interpolation Enabled)
Latency (4ϫ Interpolation Enabled)
Additional Latency (Hilbert Filter Enabled)
Additional Latency (Coarse Modulation Enabled)
Additional Latency (Fine Modulation Enabled)
Output Settling Time (TST) (to 0.1%)
Specifications subject to change without notice.
Temp
NA
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Full
Full
Full
Full
Full
Full
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Test
Level
NA
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
AD9860/AD9862
Min Typ Max
5
2.8 4
32 128
50
3
3
5.2
0.2
16
30
30
1
25
0
25
0
30
1.25
3
10
8
3
8
7
3
30
72
36
5
8
35
Unit
mA
mA
mA
mA
Unit
Clock Cycles
ns
MHz
%
ns
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
ns
ns
MHz
V
Bits
ms
V
Bits
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ns
–4– REV. 0

4페이지










AD9862 전자부품, 판매, 대치품
AD9860/AD9862
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
Receive Pins
68/7079
80/8291
92
D0A to
D9A/D11A
D0B to
D9B/D11B
RxSYNC
98, 99, AVDD
104, 105,
117, 118,
123, 124,
100, 103, AGND
106, 109,
110, 112,
113, 116,
119, 122,
101 REFT_B
102 REFB_B
107 VIN+B
108 VINB
111 VREF
114 VINA
115 VIN+A
120 REFB_A
121 REFT_A
10-/12-Bit ADC Output of
Receive Channel A
10-/12-Bit ADC Output of
Receive Channel B
Synchronization Clock for
Channel A and Channel B Rx Paths
Analog Supply Pins
Analog Ground Pins
Top Reference Decoupling for
Channel B ADC
Bottom Reference Decoupling
for Channel B ADC
Receive Channel B Differential (+) Input
Receive Channel B Differential (؊) Input
Internal ADC Voltage Reference
Receive Channel A Differential (؊) Input
Receive Channel A Differential (+) Input
Bottom Reference Decoupling for
Channel A ADC
Top Reference Decoupling for
Channel A ADC
Transmit Pins
18, 20
23, 32
AVDD
Analog Supply Pins
19, 24, AGND
27, 28, 31
Analog Ground Pins
21
REFIO
Reference Output, 1.2 V Nominal
22
FSADJ
Full-Scale Current Adjust
25 IOUTA Transmit Channel A DAC
Differential (؊) Output
26 IOUT+A Transmit Channel A DAC
Differential (+) Output
29 IOUT+B Transmit Channel B DAC
Differential (+) Output
30 IOUTB Transmit Channel B DAC
Differential (؊) Output
3748/50 Tx11/Tx13 12-/14-Bit Transmit DAC Data
to Tx0
(Interleaved Data when Required)
51 TxSYNC Synchronization Input for Transmitter
62 MODE/ Configures Default Timing Mode,
TxBLANK* Controls Tx Digital Power Down
*The logic level of the Mode/TxBLANK pin at power up defines the default timing
mode; a logic low configures Normal Operation, logic high configures Alternate
Operation Mode.
Pin No. Mnemonic
Function
Clock Pins
10
11, 16
12
13
14
15
17
64
DLL_Lock
AGND
NC
AVDD
OSC1
OSC2
CLKSEL
CLKOUT2
65 CLKOUT1
DLL Lock Indicator Pin
DLL Analog Ground Pins
No Connect
DLL Analog Supply Pin
Single Ended Input Clock
(or Crystal Oscillator Input)
Crystal Oscillator Input
Controls CLKOUT1 Rate
Clock Output Generated from Input
Clock (DLL Multiplier Setting
and CLKOUT2 Divide Factor)
Clock Output Generated from
Input Clock (1ϫ if CLKSEL = 1
or /2 if CLKSEL = 0)
Various Pins
1 AUX_ADC_A1 Auxiliary ADC A Input 1
3, 4, 13 AVDD
Analog Power Pins
2, 9 AGND
Analog Ground Pins
5
SIGDELT
Digital Output from
Programmable Sigma-Delta
6 AUX_DAC_A Auxiliary DAC A Output
7 AUX_DAC_B Auxiliary DAC B Output
8 AUX_DAC_C Auxiliary DAC C Output
33, 36, 53, DVDD
59, 61, 66,
93
Digital Power Supply Pin
34, 35, 52, DGND
58, 60, 67,
94
Digital Ground Pin
54 SCLK
Serial Bus Clock Input
55 SDO
Serial Bus Data Bit
56 SDIO
Serial Bus Data Bit
57 SEN
Serial Bus Enable
63
RESETB
Reset (SPI Registers and Logic)
95 AUX_SPI_do Optional Auxiliary ADC Serial Bus
Data Out Bit
96 AUX_SPI_clk Optional Auxiliary ADC Serial Bus
Data Out Latch Clock
97 AUX_SPI_csb Optional Auxiliary ADC Serial Bus
Chip Select Bit
128 AUX_ADC_A2 Auxiliary ADC A Input 2
126 AUX_ADC_B1 Auxiliary ADC B Input 1
125 AUX_ADC_B2 Auxiliary ADC B Input 2
127 AUX_ADC_REF Auxiliary ADC Reference
REV. 0
–7–

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