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PDF AD9864 Data sheet ( Hoja de datos )
| Número de pieza | AD9864 | |
| Descripción | IF Digitizing Subsystem | |
| Fabricantes | Analog Devices | |
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Data Sheet
IF Digitizing Subsystem
AD9864
FEATURES
GENERAL DESCRIPTION
10 MHz to 300 MHz input frequency
6.8 kHz to 270 kHz output signal bandwidth
7.5 dB single sideband noise figure (SSB NF)
−7.0 dBm input third-order intercept (IIP3)
AGC free range up to −34 dBm
12 dB continuous AGC range
16 dB front-end attenuator
Baseband I/Q 16-bit (or 24-bit) serial digital output
LO and sampling clock synthesizers
Programmable decimation factor, output format, AGC, and
synthesizer settings
370 Ω input impedance
2.7 V to 3.6 V supply voltage
Low current consumption: 17 mA
48-lead LFCSP package
APPLICATIONS
The AD98641 is a general-purpose IF subsystem that digitizes a
low level, 10 MHz to 300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864
consists of a low noise amplifier (LNA), a mixer, a band-pass Σ-∆
analog-to-digital converter (ADC), and a decimation filter with
programmable decimation factor. An automatic gain control
(AGC) circuit gives the AD9864 12 dB of continuous gain
adjustment. Auxiliary blocks include both clock and local
oscillator (LO) synthesizers.
The high dynamic range of the AD9864 and inherent antialiasing
provided by the band-pass Σ-∆ converter allow the device to cope
with blocking signals up to 95 dB stronger than the desired signal.
This attribute often reduces the cost of a radio by reducing IF
filtering requirements. Also, it enables multimode radios of varying
channel bandwidths, allowing the IF filter to be specified for the
largest channel bandwidth.
Multimode narrow-band radio products
Analog/digital UHF/VHF FDMA receivers
TETRA, APCO25, GSM/EDGE
Portable and mobile radio products
SATCOM terminals
The SPI port programs numerous parameters of the AD9864,
allowing the device to be optimized for any given application.
Programmable parameters include synthesizer divide ratios, AGC
attenuation and attack/decay time, received signal strength level,
decimation factor, output data format, 16 dB attenuator, and the
selected bias currents.
The AD9864 is available in a 48-lead LFCSP package and operates
from a single 2.7 V to 3.6 V supply. The total power consumption
is typically 56 mW and a power-down mode is provided via
serial interfacing.
FUNCTIONAL BLOCK DIAGRAM
MXOP MXON IF2P IF2N GCP GCN
–16dB
DAC AGC
AD9864
IFIN
LNA
FREF
Σ-Δ ADC
DECIMATION
FILTER
FORMATTING/SSI
CONTROL LOGIC
DOUTA
DOUTB
FS
CLKOUT
LO
SYN
CLK SYN
VOLTAGE
REFERENCE
SPI
IOUTL
LOP LON
LO VCO AND
LOOP FILTER
IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB
LOOP FILTER
Figure 1.
1 Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9864
Parameter
OVERALL
Analog Supply Voltage (VDDA, VDDF, VDDI)
Digital Supply Voltage (VDDD, VDDC, VDDL)
Interface Supply Voltage (VDDH)6
Charge Pump Supply Voltage (VDDP, VDDQ)
Total Current
Operation Mode7
Standby
OPERATING TEMPERATURE RANGE
Temperature Test Level Min
Full VI 2.7
Full VI 2.7
Full VI 1.8
Full VI 2.7
Full VI
Full VI
−40
Typ
3.0
3.0
5.0
17
0.01
1 This includes 0.9 dB loss of matching network.
2 AGC with DVGA enabled.
3 Measured in 10 kHz bandwidth.
4 Programmable in 0.67 mA steps.
5 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
6 VDDH must be less than VDDD + 0.5 V.
7 Clock VCO off and additional 0.7 mA with VGA at maximum attenuation.
Data Sheet
Max Unit
3.6 V
3.6 V
3.6 V
5.5 V
mA
mA
+85 °C
Rev. A | Page 4 of 47
5 Page 
AD9864
Data Sheet
VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 3.0 V , VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO =
107.4 MHz, fREF = 16.8 MHz, TA=25 Co, LO and CLK synthesizer disabled, unless otherwise noted.
9.0 0 –12
8.8 –10 –15
8.6
–20 –18
8.4
8.2 –30 –21
NF
8.0 –40 –24
7.8 –50 –27
IMD
7.6
–60 –30
7.4
7.2 –70 –33
7.0
–20 –15 –10
–5
0
LO DRIVE (dBm)
–80
5
Figure 9. Noise Figure and IMD vs. LO Drive (VDDx = 3.0 V)
–36
–36 –33 –30 –27 –24 –21 –18 –15 –12 –9 –6 –3 –0
IFIN (dBm)
Figure 12. Gain Compression vs. IFIN with 16 dB LNA Attenuator Enabled
0
ADC DOES NOT GO INTO
HARD COMPRESSION
–2 3.6V
–4 3.3V
–6
3.0V
–8
2.7V
–10
–12
–14
–30
–28 –26 –24 –22 –20 –18
IFIN (dBm)
Figure 10. Gain Compression vs. IFIN
–16
–14
–55 –15
–61
PIN
–67
2.7V
–73
–18
–21
–24
–79 –27
3.0V
–85 –30
3.3V
–91 –33
–97
–103
3.6V
–36
–39
–109
–42
–115
–45
–51 –48 –45 –42 –39 –36 –33 –30
IFIN (dBm)
Figure 13. IMD vs. IFIN
10.0 10.0
9.5
16-BIT
I/Q DATA
9.0
8.5
16-BIT
I/Q DATA WITH
DVGA ENABLED
9.5
16-BIT
DATA
9.0
8.5
16-BIT DATA
WITH DVGA ENABLED
8.0
24-BIT
I/Q DATA
7.5
10
100
CHANNEL BANDWIDTH (kHz)
Figure 11. Noise Figure vs. Bandwidth
(Minimum Attenuation, fCLK = 13 MSPS)
1000
8.0
24-BIT
DATA
7.5
10
100
CHANNEL BANDWIDTH (kHz)
Figure 14. Noise Figure vs. Bandwidth
(Minimum Attenuation, fCLK = 18 MSPS)
1000
Rev. A | Page 10 of 47
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9864.PDF ] | |
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