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PDF AD9873 Data sheet ( Hoja de datos )
| Número de pieza | AD9873 | |
| Descripción | Analog Front End Converter for Set-Top Box/ Cable Modem | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9873 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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a
Analog Front End Converter for
Set-Top Box, Cable Modem
AD9873
FEATURES
Low-Cost 3.3 V CMOS Analog Front End Converter for
MCNS-DOCSIS, DVB, DAVIC-Compliant
Set-Top Box, Cable Modem Applications
232 MHz Quadrature Digital Upconverter
DC to 65 MHz Output Bandwidth
12-Bit Direct IF D/A Converter (TxDAC+®)
Programmable Reference Clock Multiplier (PLL)
Direct Digital Synthesis
Interpolator
SIN(x)/x Compensation Filter
Four Programmable, Pin-Selectable Modulator Profiles
Single-Tone Mode for Frequency Synthesis Applications
12-Bit, 33 MSPS Sampling Direct IF A/D Converter with
Auxiliary Automatic Clamp Video Input Multiplexer
10-Bit, 33 MSPS Sampling Direct IF A/D Converter
Dual 8-Bit, 16.5 MSPS Sampling IQ A/D Converter
Two Independently Programmable Sigma-Delta
Converters
Direct Interface to AD8321/AD8323 PGA Cable Driver
Programmable Frequency Output
Power-Down Modes
APPLICATIONS
Cable and Satellite Systems
PC Multimedia
Digital Communications
Data and Video Modems
Cable Modem
Set-Top Boxes
Powerline Modem
Broadband Wireless Communication
FUNCTIONAL BLOCK DIAGRAM
Tx IQ
Tx SYNC
SERIAL ITF
PROFILE
Tx INTERPOLATOR
FILTER
PLL DDS
AD9873
COS
INV 12
SINC
DAC
SIN
3
4 12
2
CONTROL FUNCTIONS
12
Rx IQ
Rx IF
Rx SYNC
Rx
8
ADC
8
ADC
10
ADC
Tx
CA
SDELTA0
SDELTA1
REF CLK
IIN
QIN
IF10
12 ADC
MUX
IF12
VIDEO
GENERAL DESCRIPTION
The AD9873 integrates a complete 232 MHz quadrature
digital transmitter and a multichannel receiver with four high-
performance analog-to-digital converters (ADC) for various
video and digital data signals. The AD9873 is designed for cable
modem set-top box applications, where cost, size, power dissi-
pation, and dynamic performance are critical attributes. A single
external crystal is used to control all internal conversion and
data processing cycles.
The transmit section of the AD9873 includes a high-speed
direct digital synthesizer (DDS), a high-performance, high-speed
12-bit digital-to-analog converter (DAC), programmable clock
multiplier circuitry, digital filters, and other digital signal
processing functions, to form a complete quadrature digital
up-converter device.
On the receiver side, two 8-bit ADCs are optimized for IQ
demodulated “out-of band” signals. An on-chip 10-bit ADC
is typically used as a direct IF input of 256 QAM modulated
signals in cable modem applications. A second direct IF input
and an auxiliary video input with automatic programmable clamp
function are multiplexed to a high-performance 12-bit video ADC.
The chip’s programmable sigma-delta modulated outputs and
an output clock may be used to control external components
such as programmable gain amplifiers (PGA) and mixer stages.
Three pins provide a direct interface to the AD8321/AD8323
programmable gain amplifier (PGA) cable driver.
The AD9873 is available in a space-saving 100-lead MQFP package.
TxDAC+ is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
Parameter
12-BIT ADC CHARACTERISTICS (Continued)
Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz)
Signal-to-Noise and Distortion Ratio (SINAD)
Signal-to-Noise and Distortion Ratio (SINAD)3
Effective Number of Bits (ENOB)
Effective Number of Bits (ENOB)3
Signal-to-Noise Ratio (SNR)
Signal-to-Noise Ratio (SNR)3
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD)3
Spurious Free Dynamic Range (SFDR)
Spurious Free Dynamic Range (SFDR)3
Differential Phase
Differential Gain
VIDEO CLAMP INPUT
Input Voltage Range
Clamp Current Positive
Clamp Droop Current
Clamp Level Offset Programming Range
Clamp Level Resolution
Carrier Rejection Filter Bandwidth (–3 dB)
Dynamic Performance (AIN = –0.5 dB FS, f = 5 MHz)
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
Differential Phase
Differential Gain
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation
(5 MHz Analog Output)
Isolation Between Tx and 8-Bit ADCs
Isolation Between Tx and 10-Bit ADC
Isolation Between Tx and 12-Bit ADC
ADC-to-ADC Isolation
(AIN = –0.5 dB FS, f = 5 MHz)
Isolation Between IF12 and Video
Isolation Between IF10 and IF12
Isolation Between Q in and IF10
Isolation Between Q in and I Inputs
TIMING CHARACTERISTICS (20 pF Load)
Wake-Up Time
Minimum RESET Pulsewidth Low (tRL)
Digital Output Rise/Fall Time
Tx/Rx Interface
MCLK Frequency (fMCLK)
TxSYNC/TxIQ Set Up Time (tSU)
TxSYNC/TxIQ Hold Time (tHD)
RxSYNC/RxIQ/IF to Valid Time (tTV)
RxSYNC/RxIQ/IF Hold Time (tHT)
Serial Control Bus
SCLK Frequency (fSCLK)
Clock Pulsewidth High (tPWH)
Clock Pulsewidth Low (tPWL)
Clock Rise/Fall Time
Data/Chip-Select Setup Time (tDS)
Data Hold Time (tDH)
Data Valid Time (tDV)
REV. 0
Temp
Test
Level Min
Typ
AD9873
Max Unit
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25ЊC
25ЊC
Full
25ЊC
25ЊC
25ЊC
25ЊC
25ЊC
Full
Full
Full
Full
Full
25°C
25°C
III
IV
III
IV
III
IV
III
IV
III
IV
IV
IV
IV
IV
IV
III
IV
IV
IV
IV
IV
IV
IV
IV
IV
62.3 65
67.4
10.0 10.5
10.8
63.3 65.3
67.4
–77.6
–77.6
65.7 80
80
<0.1
<1
2
1.3
2
256 512
16
0.6
52
8.34
61.0
–53.0
55.0
<0.1
<8
–65.4
dB
dB
Bits
Bits
dB
dB
dB
dB
dB
dB
Degree
LSB
2032
V
mA
A
LSB
LSB
MHz
dB
Bits
dB
dB
dB
Degree
LSB
25ЊC
25ЊC
25ЊC
IV
IV
IV
>80
>85
>90
25ЊC
25ЊC
25ЊC
25ЊC
III
IV
IV
IV
70 >70
>80
>80
>70
N/A N/A
N/A N/A
5
25ЊC
III
2.8
25ЊC
25ЊC
25ЊC
25ЊC
25ЊC
III
III
III
III
III
3
3
0.2
Full III
Full III 30
Full III 30
Full III
Full III 25
Full III 0
Full III
–5–
dB
dB
dB
dB
dB
dB
dB
200 tMCLK Cycles
tMCLK Cycles
4 ns
66 MHz
ns
ns
5.2 ns
ns
15 MHz
ns
ns
1 ms
ns
ns
30 ns
5 Page 
AD9873
Table I. Register Map
Address
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
(Hex) Type
00
SDIO
LSB/MSB RESET
OSC IN
OSC IN
OSC IN
OSC IN
OSC IN
10
rw
Bidirectional First
Multiplier Multiplier Multiplier Multiplier Multiplier
M <4>
M <3>
M <2>
M <1>
M <0>
01 PLL
OSC IN
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
09
rw
Lock
Divider
Divider
Divider
Divider
Divider
Divider
Divider
Detect
N = 3 (4)
R <5>
R <4>
R <3>
R <2>
R <1>
R <0>
02
Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down 00
rw
PLL
DAC Tx
Digital Tx 12-Bit ADC Reference 10-Bit ADC Reference 8-Bit ADC
12-Bit ADC
10-Bit ADC
03 Sigma-Delta Output 0 Control Word <3:0> LSB 0 0 0 0 00 rw ⌺⌬
04
Sigma-Delta Output 0 Control Word <11:4> MSB
00 rw ⌺⌬
05 Sigma-Delta Output 1 Control Word <3:0> LSB 0 0 0 0 00 rw ⌺⌬
06
Sigma-Delta Output 1 Control Word <11:4> MSB
00 rw ⌺⌬
07 Video Input
Enable
Clamp Level Control for Video Input <6:0>
20 rw ADC
08 ADC Clock 0
Select
ADC Clock 0
0
0
Test Test 00 rw ADC
Select
12-Bit ADC 10-Bit ADC
09 0 0 0 0 0 0 0 0 00 rw
0A 0 0 0 0 0 0 0 0 00 rw
0B 0 0 0 0 0 0 0 0 00 rw
0C 0 0 0 0
Version <3:0>
0X r
0D 0 0 0 0 0 0 0 0 00 r
0E 0 0 0 0 0 0 0 0 00 r
0F 0
0
Profile
Profile
0
Bypass
Spectral
Single-Tone 00
rw Tx
Select <1> Select <0>
Inv. Sinc
Inversion Tx Tx Mode
Tx Filter
10 Tx Frequency Turning Word Profile 0 <7:0>
00 rw Tx
11 Tx Frequency Turning Word Profile 0 <15:8>
00 rw Tx
12 Tx Frequency Turning Word Profile 0 <23:16>
00 rw Tx
13
Cable Driver Amplifier Gain Control Profile 0 <7:0>
00 rw Tx
14 Tx Frequency Turning Word Profile 1 <7:0>
00 rw Tx
15 Tx Frequency Turning Word Profile 1 <15:8>
00 rw Tx
16 Tx Frequency Turning Word Profile 1 <23:16>
00 rw Tx
17
Cable Driver Amplifier Gain Control Profile 1 <7:0>
00 rw Tx
18 Tx Frequency Turning Word Profile 2 <7:0>
00 rw Tx
19 Tx Frequency Turning Word Profile 2 <15:8>
00 rw Tx
1A Tx Frequency Turning Word Profile 2 <23:16>
00 rw Tx
1B
Cable Driver Amplifier Gain Control Profile 2 <7:0>
00 rw Tx
1C Tx Frequency Turning Word Profile 3 <7:0>
00 rw Tx
1D Tx Frequency Turning Word Profile 3 <15:8>
00 rw Tx
1E Tx Frequency Turning Word Profile 3 <23:16>
00 rw Tx
1F
Cable Driver Amplifier Gain Control Profile 3 <7:0>
00 rw Tx
“0” register bits should not be programmed with 1.
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9873.PDF ] | |
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