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AD9901 데이터시트 PDF




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부품번호 AD9901 기능
기능 Ultrahigh Speed Phase/Frequency Discriminator
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AD9901 데이터시트, 핀배열, 회로
a
FEATURES
Phase and Frequency Detection
ECL/TTL/CMOS Compatible
Linear Transfer Function
No “Dead Zone”
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Low Phase Noise Reference Loops
Fast-Tuning “Agile” IF Loops
Secure “Hopping” Communications
Coherent Radar Transmitter/Receiver Chains
Ultrahigh Speed
Phase/Frequency Discriminator
AD9901
PHASE-LOCKED LOOP
REFERENCE
INPUT
AD9901
LOW-
PASS
FILTER
VCO
OSCILLATOR
OUTPUT
1/N
OPTIONAL 1/N PRESCALER
TYPICAL OF DIGITAL PLLs
GENERAL DESCRIPTION
The AD9901 is a digital phase/frequency discriminator capable
of directly comparing phase/frequency inputs up to 200 MHz.
Processing in a high speed trench-oxide isolated process, com-
bined with an innovative design, gives the AD9901 a linear
detection range, free of indeterminate phase detection zones
common to other digital designs.
With a single +5 V supply, the AD9901 can be configured to
operate with TTL or CMOS logic levels; it can also operate
with ECL inputs when operated with a –5.2 V supply. The
open-collector outputs allow the output swing to be matched to
post-filtering input requirements. A simple current setting resis-
tor controls the output stage current range, permitting a reduc-
tion in power when operated at lower frequencies.
A major feature of the AD9901 is its ability to compare
phase/frequency inputs at standard IF frequencies without
prescalers. Excessive phase uncertainty which is common with
standard PLL configurations is also eliminated. The AD9901
provides the locking speed of traditional phase/frequency dis-
criminators, with the phase stability of analog mixers.
The AD9901 is available as a commercial temperature range
device, 0°C to +70°C, and as a military temperature device,
–55°C to +125°C. The commercial versions are packaged in a
14-lead ceramic DIP and a 20-lead PLCC.
The AD9901 Phase/Frequency Discriminator is available in
versions compliant with MIL-STD-883. Refer to the Analog
Devices Military Products Databook or current AD9901/883B
data sheet for specifications.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
INPUT
OSCILLATOR
INPUT
DQ
REFERENCE
INPUT
FLIP-FLOP
Q
DQ
OSCILLATOR
INPUT
FLIP-FLOP
Q
XOR
DQ
REFERENCE
FREQUENCY
DISCRIMINATOR
FLIP-FLOP
RQ
DS
Q
OSCILLATOR
FREQUENCY
DISCRIMINATOR
FLIP-FLOP
Q
OUTPUT
OUTPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999




AD9901 pdf, 반도체, 판매, 대치품
AD9901
TTL/CMOS MODE FUNCTIONAL PIN DESCRIPTIONS
GROUND
Ground connections for AD9901. Connect
all grounds together and to low impedance
ground plane as close to the device as
possible.
+VS Positive supply connection; nominally +5.0 V
for TTL operation.
BIAS
VCO INPUT
OUTPUT
Connect to +VS (+5 V) for TTL operation.
TTL compatible input; normally connected
to the VCO output signal. VCO INPUT and
REFERENCE INPUT are equivalent to one
another.
The noninverted output. In TTL/CMOS
mode, the output swing is approximately
+3.2 V to +5 V.
RSET
OUTPUT
External RSET connection. The current
through the RSET resistor is equal to the maxi-
mum full-scale output current. RSET should
be connected to ground through an external
resistor in TTL mode. ISET = 0.47 V/RSET =
ILOAD (max).
The inverted output. In TTL/CMOS mode,
the output swing is approximately +3.2 V to
+5 V.
REFERENCE
INPUT
TTL compatible input, normally connected
to the reference input signal. The VCO
INPUT and the REFERENCE INPUT are
equivalent.
+VS
REFERENCE
R2
OUTPUT +VS OUTPUT
R1
RSET
ECL MODE FUNCTIONAL PIN DESCRIPTIONS
–VS Negative supply connection, nominally
–5.2 V for ECL operation.
BIAS
VCO INPUT
Connect to –5.2 V for ECL operation.
Inverted side of ECL compatible differential
input, normally connected to the VCO output
signal.
VCO INPUT
Noninverted side of ECL-compatible
differential input, normally connected to the
VCO output signal.
OUTPUT
The noninverted output. In ECL mode, the
output swing is approximately 0 V to –1.8 V.
GROUND
Ground connections for AD9901. Connect
all grounds together and to low-impedance
ground plane as close to the device as
possible.
RSET
OUTPUT
External RSET connection. The current
through the RSET resistor is equal to the maxi-
mum full-scale output current. RSET should
be connected to –VS through an external
resistor in ECL mode. ISET = 0.47 V/RSET =
ILOAD (max).
The inverted output. In ECL mode, the out-
put swing is approximately 0 V to –1.8 V.
REFERENCE
INPUT
REFERENCE
INPUT
Noninverted side of ECL-compatible
differential input, normally connected to the
reference input signal. The VCO INPUT and
the REFERENCE INPUT are equivalent to
one another.
Inverted side of ECL-compatible differential
input, normally connected to the reference
input signal. The VCO INPUT and the
REFERENCE INPUT are equivalent.
REFERENCE REFERENCE
INPUT
INPUT –VS
R2
OUTPUT
–VS
R1
RSET
AD9901
AD9901
REG
BIAS
+VS
VCO OUTPUT
INPUT
R3
+VS
+VS
Figure 1. TTL Mode (Based on DIP Pinouts)
REG
BIAS
–VS
VCO VCO –VS OUTPUT
INPUT INPUT
R3
Figure 2. ECL Mode (Based on DIP Pinouts)
–4– REV. B

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AD9901 전자부품, 판매, 대치품
500mV
100
90
500mV
100
90
500mV
100
90
AD9901
10 10 10
0% 0% 0%
200ns
200ns
5ns
Figure 8. AD9901 Output Waveform
(FO << FI)
Figure 9. AD9901 Output Waveform
(FO >> FI)
Figure 10. AD9901 Output Waveform
(FO = FI = 50 MHz)
It is important to note that the slope of the transfer function is
constant near its midpoint. Many digital phase comparators have
an area near the lock point where their gain goes to zero, result-
ing in a “dead zone.” This causes increased phase noise (jitter) at
the lock point.
The AD9901 avoids this dead zone by shifting it to the end-
points of the transfer curve, as indicated in Figure 7. The in-
creased gain at either end increases the effective error signal to
pull the oscillator back into the linear region. This does not
affect phase noise, which is far more dependent upon lock region
characteristics.
It should be noted, however, that as frequency increases, the
linear range is decreased. At the ends of the detection range, the
reference and oscillator inputs approach phase alignment. At this
point, slew rate limiting in the detector effectively increases
phase gain. This decreases the linear detection by nominally
3.6 ns. Therefore, the typical detection range can be found by
calculating [(1/F – 3.6 ns)/(1/F)] × 360°. As an example, at
200 MHz the linear phase detection range is ±50°.
Away from lock, the AD9901 becomes a frequency discrimina-
tor. Any time either the reference or oscillator input occurs twice
before the other, the Frequency High or Frequency Low flip-flop
is clocked to logic LOW. This overrides the XOR output and
holds the output at the appropriate level to pull the oscillator
toward the reference frequency. Once the frequencies are within
the linear range, the phase detector circuit takes over again.
Combining the frequency discriminator with the phase detector
eliminates locking to a harmonic of the reference.
Figure 8 shows the effect of the “Frequency Low” flip-flop when
the oscillator frequency is much lower than the reference input.
The narrow pulses, which result from cycles when two positive
reference-input transitions occur before a positive VCO edge,
increase the dc mean value. Figure 9 illustrates the inverse effect
when the “Frequency High” flip-flop reacts to a much higher
VCO frequency.
Figure 10 shows the output waveform at lock for 50 MHz opera-
tion. This output results when the phase difference between
reference and oscillator is approximately – πRad.
AD9901 APPLICATIONS
The figure below illustrates a phase-locked loop (PLL) system
utilizing the AD9901. The first step in designing this type of
circuit is to characterize the VCO’s output frequency as a func-
tion of tuning voltage. The transfer function of the oscillator in
the diagram is shown in Figure 11.
165
155
145
135
125
115
105
95
85
75
65
–1
0 12 3 4 5
VARACTORS TUNING VOLTAGE – Volts
6
Figure 11. VCO Frequency vs. Voltage
Next, the range of frequencies over which the VCO is to operate
is examined to assure that it lies on a linear portion of the transfer
curve. In this case, frequencies from 100 MHz to 120 MHz
result from tuning voltages of approximately +1.5 V to +2.5 V.
Because the nominal output swing of the AD9901 is 0 V to –1.8 V,
an inverting amplifier with a gain of 2 follows the loop filter.
As shown in the illustration, a simple passive RC low-pass filter
made up of two resistors and a tantalum capacitor eliminates the
need for an expensive high speed op amp active-filter design. In
this passive-filter second-order-loop system, where n = 2, the
damping factor is equal to:
δ = 0.5 [KOKd /n(τ1 + τ2)]1/2 [τ2 + (n/KOKd)]
and the values for τ1 and τ2 are the low-pass filter’s time con-
stants R1C and R2C. The gain of 2 of the inverting stage, when
combined with the phase detector’s gain, gives:
Kd = 0.572 V/RAD
With KO = 115.2 MRAD/s/V, τ1 equals 1.715s, and τ2 equals
3.11 × 10–4s for the required damping factor of 0.7. The illus-
trated values of 30 (R1), 160 (R2), and 10 µF (C) in the
diagram approximate these time constants.
The gain of the RC filter is:
VO/VI = (1 + sR2C)/[1 + s(R1 + R2)C].
Where KOKd >> ωn, the system’s natural frequency:
ωn = [KOK d/n(τ1 + τ2)]1/2 = 4.5 kHz.
For general information about phase-locked loop design, the
user is advised to consult the following references: Gardner,
Phase-Lock Techniques (Wiley); or Best, Phase Locked Loops
(McGraw-Hill).
REV. B
–7–

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AD9901

Ultrahigh Speed Phase/Frequency Discriminator

Analog Devices
Analog Devices

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