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PDF AD9945 Data sheet ( Hoja de datos )
| Número de pieza | AD9945 | |
| Descripción | Complete 12-Bit 40 MHz CCD Signal Processor | |
| Fabricantes | Analog Devices | |
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FEATURES
40 MSPS Correlated Double Sampler (CDS)
6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Optical Black Clamp Circuit
Preblanking Function
12-Bit 40 MSPS A/D Converter
No Missing Codes Guaranteed
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power:160 mW @ 3 V Supply
Space-Saving 32-Lead 5 mm ؋ 5 mm LFCSP
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
PC Cameras
Portable CCD Imaging Devices
CCTV Cameras
Complete 12-Bit 40 MHz
CCD Signal Processor
AD9945
GENERAL DESCRIPTION
The AD9945 is a complete analog signal processor for CCD
applications. It features a 40 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9945’s signal chain
consists of a correlated double sampler (CDS), a digitally con-
trolled variable gain amplifier (VGA), a black level clamp, and a
12-bit A/D converter.
The internal registers are programmed through a 3-wire serial digital
interface. Programmable features include gain adjustment, black
level adjustment, input clock polarity, and power-down modes.
The AD9945 operates from a single 3 V power supply, typi-
cally dissipates160 mW, and is packaged in a space-saving
32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
PBLK
AD9945
CCDIN
CDS
6dB TO 40dB
VGA
BAND GAP
REFERENCE
12-BIT
ADC
DRVDD
DRVSS
12
DOUT
AVDD
AVSS
10
CONTROL
REGISTERS
DIGITAL
INTERFACE
CLP
CLPOB
INTERNAL
TIMING
DVDD
DVSS
SL SCK SDATA
SHP SHD DATACLK
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113
www.analog.com
©2013 Analog Devices, Inc. All rights reserved.
1 page  
AD9945
TIMING SPECIFICATIONS (CL = 20 pF, fSAMP = 40 MHz, CCD Mode Timing in Figures 8 and 9, Serial Timing in Figures 4 and 5.)
Parameter
Symbol
Min
Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulse Width
SHP Pulse Width
SHD Pulse Width
CLPOB Pulse Width*
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
DATA OUTPUTS
Output Delay
Pipeline Delay
tCONV
tADC
tSHP
tSHD
tCOB
tS1
tS2
tID
tOD
25
10
2
11.25
12.5
6.25
6.25
20
6.25
12.5
3
9.5
10
ns
ns
ns
ns
Pixels
ns
ns
ns
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
fSCLK
tLS
tLH
tDS
tDH
10
10
10
10
10
MHz
ns
ns
ns
ns
*Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
To Min Max
Unit
AVDD
DVDD
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, PBLK
SCK, SL, SDATA
REFT, REFB, CCDIN
Junction Temperature
Lead Temperature
(10 sec)
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 AVDD + 0.3 V
150 °C
300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-Lead LFCSP Package
θJA = 27.7 °C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9945 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. C
5 Page 
AD9945
0.1F CCDIN
DC RESTORE
CDS
6dB TO 40dB
VGA
INTERNAL
VREF
2V FULL SCALE
12-BIT
ADC
12
DOUT
10
VGA GAIN
REGISTER
8-BIT
DAC
OPTICAL BLACK
CLAMP
DIGITAL
FILTERING
8
CLAMP LEVEL
REGISTER
Figure 6. CCD Mode Block Diagram
CLPOB
CIRCUIT DESCRIPTION AND OPERATION
The AD9945 signal processing chain is shown in Figure 6. Each
processing step is essential in achieving a high quality image from
the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V to be compatible with the 3 V single supply
of the AD9945.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 8 illustrates how the two CDS clocks, SHP and
SHD, are used to sample the reference level and data level of
the CCD signal, respectively. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (tID) of 3 ns is caused by internal
propagation delays.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with the
fixed black level reference, selected by the user in the clamp
level register. The resulting error signal is filtered to reduce
noise, and the correction value is applied to the ADC input
through a D/A converter. Normally, the optical black clamp
loop is turned on once per horizontal line, but this loop can be
updated more slowly to suit a particular application. If external
digital clamping is used during the postprocessing, the AD9945
optical black clamping may be disabled using Bit D3 in the
operation register (see the Serial Interface Timing and Internal
Register Description sections).
When the loop is disabled, the clamp level register may still be
used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 9. The CLPOB pulse should
be placed during the CCD’s optical black pixels. It is recom-
mended that the CLPOB pulse be used during valid CCD dark
pixels. The CLPOB pulse should be a minimum of 20 pixels wide
to minimize clamp noise. Shorter pulse widths may be used, but
clamp noise may increase and the loop’s ability to track low fre-
quency variations in the black level will be reduced.
A/D Converter
The ADC uses a 2 V input range. Better noise performance results
from using a larger ADC full-scale range. The ADC uses a
pipelined architecture with a 2 V full-scale input for low noise
performance.
Variable Gain Amplifier
The VGA stage provides a gain range of 6 dB to 40 dB, program-
mable with 10-bit resolution through the serial digital interface.
The minimum gain of 6 dB is needed to match a 1 V input signal
with the ADC full-scale range of 2 V. A plot of the VGA gain curve
is shown in Figure 7.
VGA Gain(dB) = (VGA Code × 0.035 dB) + 5.3 dB
42
36
30
24
18
12
6
0 127 255 383 511 639 767 895 1023
VGA GAIN REGISTER CODE
Figure 7. VGA Gain Curve
–10–
REV. C
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AD9945.PDF ] | |
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