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PDF AD9948 Data sheet ( Hoja de datos )
| Número de pieza | AD9948 | |
| Descripción | 10-Bit CCD Signal Processor with Precision Timing Core | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Correlated Double Sampler (CDS)
0 dB to 18 dB Pixel Gain Amplifier (PxGA®)
6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 25 MSPS A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing Core with 800 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
40-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
High Speed Digital Imaging Applications
10-Bit CCD Signal Processor with
Precision Timing™ Core
AD9948
GENERAL DESCRIPTION
The AD9948 is a highly integrated CCD signal processor for
digital still camera applications. Specified at pixel rates of up to
25 MHz, the AD9948 consists of a complete analog front end
with A/D conversion, combined with a programmable timing
driver. The Precision Timing core allows adjustment of high
speed clocks with 800 ps resolution.
The analog front end includes black level clamping, CDS, PxGA,
VGA, and a 25 MHz 10-bit A/D converter. The timing driver
provides the high speed CCD clock drivers for RG and H1–H4.
Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving 40-lead LFCSP package, the
AD9948 is specified over an operating temperature range of
–20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
CDS
0dB TO 18dB
PxGA
6dB TO 42dB
VGA
VREF
10-BIT
ADC
10
DOUT
RG
HORIZONTAL
4 DRIVERS
H1–H4
AD9948
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
HD VD
CLAMP
HBLK
CLP/PBLK
CLI
INTERNAL
REGISTERS
SL SCK SDATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION
NC 1
(LSB) D0 2
D1 3
D2 4
DRVSS 5
DRVDD 6
D3 7
D4 8
D5 9
D6 10
PIN 1
IDENTIFIER
AD9948
TOP VIEW
30 REFB
29 REFT
28 AVSS
27 CCDIN
26 AVDD
25 CLI
24 TCVDD
23 TCVSS
22 RGVDD
21 RG
AD9948
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type*
Description
2–4
5
6
7–13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1, 40
D0–D2
DRVSS
DRVDD
D3–D9
H1
H2
HVSS
HVDD
H3
H4
RGVSS
RG
RGVDD
TCVSS
TCVDD
CLI
AVDD
CCDIN
AVSS
REFT
REFB
SL
SDI
SCK
VD
HD
DVSS
DVDD
HBLK
CLP/PBLK
NC
DO
P
P
DO
DO
DO
P
P
DO
DO
P
DO
P
P
P
DI
P
AI
P
AO
AO
DI
DI
DI
DI
DI
P
P
DI
DO
Data Outputs (D0 is LSB)
Digital Driver Ground
Digital Driver Supply
Data Outputs (D9 is MSB)
CCD Horizontal Clock 1
CCD Horizontal Clock 2
H1–H4 Driver Ground
H1–H4 Driver Supply
CCD Horizontal Clock 3
CCD Horizontal Clock 4
RG Driver Ground
CCD Reset Gate Clock
RG Driver Supply
Analog Ground for Timing Core
Analog Supply for Timing Core
Master Clock Input
Analog Supply for AFE
Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)
Analog Ground for AFE
Reference Top Decoupling (Decouple with 1.0 µF to AVSS)
Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)
3-Wire Serial Load
3-Wire Serial Data Input
3-Wire Serial Clock
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground
Digital Supply
Optional HBLK Input
CLPOB or PBLK Output
Not Internally Connected
*Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–5–
5 Page 
AD9948
Address
20
21
22
23
24
25
26
27
28
Data Bit
Content
[3:0]
[23:0]
[23:0]
[23:0]
[23:0]
[7:0]
[11:0]
[11:0]
[11:0]
Default
Value (Hex)
F
FFFFFF
FFFFFF
FFFFFF
FFFFFF
0
0
FFF
FFF
FFF
Table IV. CLPOB Register Map
Name
CLPOBPOL
CLPOBTOG_0
CLPOBTOG_1
CLPOBTOG_2
CLPOBTOG_3
CLPOBSCP0
CLPOBSPTR
CLPOBSCP1
CLPOBSCP2
CLPOBSCP3
Description
Start Polarities for CLPOB Sequences 0, 1, 2, and 3.
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
CLPOB Sequence-Change-Position 0 (Hard-Coded to 0).
CLPOB Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
CLPOB Sequence-Change-Position 1.
CLPOB Sequence-Change-Position 2.
CLPOB Sequence-Change-Position 3.
Address
30
31
32
33
34
35
36
37
38
Data Bit
Content
[3:0]
[23:0]
[23:0]
[23:0]
[23:0]
[7:0]
[11:0]
[11:0]
[11:0]
Default
Value (Hex)
F
FFFFFF
FFFFFF
FFFFFF
FFFFFF
0
0
FFF
FFF
FFF
Table V. PBLK Register Map
Name
PBLKPOL
PBLKTOG_0
PBLKTOG_1
PBLKTOG_2
PBLKTOG_3
PBLKSCP0
PBLKSPTR
PBLKSCP1
PBLKSCP2
PBLKSCP3
Description
Start Polarities for PBLK Sequences 0, 1, 2, and 3.
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
PBLK Sequence-Change-Position 0 (Hard-Coded to 0).
PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
PBLK Sequence-Change-Position 1.
PBLK Sequence-Change-Position 2.
PBLK Sequence-Change-Position 3.
REV. 0
–11–
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD9948.PDF ] | |
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