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AD9952 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9952은 전자 산업 및 응용 분야에서
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기능 Direct Digital Synthesizer
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AD9952 데이터시트, 핀배열, 회로
400 MSPS 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9952
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
32-bit tuning word
Phase noise ≤ −120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP_EP package
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
High speed comparator (200 MHz toggle rate)
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generators
Test and measurement equipment
Acousto-optic device drivers
GENERAL DESCRIPTION
The AD9952 is a direct digital synthesizer (DDS) featuring a
14-bit DAC (digital-to-analog converter) and operating up to
400 MSPS. The AD9952 uses advanced DDS technology,
coupled with an internal high speed, high performance DAC to
form a digitally programmable, complete high frequency
synthesizer capable of generating a frequency-agile analog
output sinusoidal waveform at up to 200 MHz. The AD9952 is
designed to provide fast frequency hopping and fine tuning
resolution (32-bit frequency tuning word). The frequency
tuning and control words are loaded into the AD9952 via a
serial I/O port.
The AD9952 is specified to operate over the extended industrial
temperature range of −40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
PHASE
ACCUMULATOR
Z–1
32
PHASE
OFFSET
19
COS(X)
AD9952
14 DAC
14
SYSTEM
CLOCK
Z–1
DAC_RSET
IOUT
IOUT
32 14
I/O UPDATE
SYNC_CLK
REFCLK
REFCLK
0
M
U
X
SYNC
OSCILLATOR/BUFFER
ENABLE
4× TO 20×
CLOCK
MULTIPLIER
TIMING AND CONTROL LOGIC
÷ 4 CONTROL REGISTERS
M
U SYSTEM
X CLOCK
SYNC_IN
OSK
PWRDWNCTL
COMPARATOR
COMP_IN
COMP_IN
COMP_OUT
CRYSTAL OUT
I/O PORT
Figure 1.
RESET
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.




AD9952 pdf, 반도체, 판매, 대치품
AD9952
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Electrical Specifications ................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Equivalent Input/Output Circuits ................................................ 12
Theory of Operation ...................................................................... 13
Component Blocks ..................................................................... 13
REVISION HISTORY
5/09—Rev. A to Rev. B
Changes to Comparator Input Characteristics,
Hysteresis Parameter, Table 1.......................................................... 4
Changes to Pin Configuration and Function Descriptions
Section and Table 3........................................................................... 7
Changes to Table 5.......................................................................... 15
Changes to Serial Interface Port Pin Description Section ........ 22
Changes to Figure 32...................................................................... 26
Added Exposed Pad Notation to Outline Dimensions ............. 27
Changes to Ordering Guide .......................................................... 27
5/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Electrical Specifications Section ................................ 3
Changes to Figure 3.......................................................................... 9
Changes to Serial Port Operation Section................................... 20
Inserted Figure 24, Figure 25, and Figure 26 .............................. 21
12/03—Revision 0: Initial Version
Control Register Bit Descriptions ............................................ 16
Other Register Descriptions ..................................................... 18
Modes of Operation ................................................................... 18
Programming Features .............................................................. 18
Synchronizing Multiple AD9952s............................................ 20
Serial Port Operation................................................................. 20
Power-Down Functions............................................................. 23
Layout Considerations................................................................... 25
Suggested Application Circuits..................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
Rev. B | Page 2 of 28

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AD9952 전자부품, 판매, 대치품
AD9952
Parameter
Wake-Up Time6
Minimum Reset Pulse Width High
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, SYNC_CLK Hold Time
Latency
I/O UPDATE to Frequency Change Propagation Delay
I/O UPDATE to Phase Offset Change Propagation Delay
I/O UPDATE to Amplitude Change Propagation Delay
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION8
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution9
Temp
Full
Full
Full
Full
Full
Min
5
4
6
0
25°C 24
25°C 24
25°C 16
25°C 1.25
25°C
25°C 2.2
25°C
25°C
25°C
25°C
25°C 1.35
25°C
25°C 2.8
25°C
25°C
25°C
25°C
25°C 62.5
25°C 100
25°C
Typ Max
1
0.6
0.8
3 12
12
2
0.4
0.4
162 171
150 160
20 27
±1
Unit
ms
SYSCLK cycles7
ns
ns
ns
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
V
V
V
V
µA
µA
pF
V
V
V
V
mW
mW
mW
MHz
MHz
SYSCLK cycles
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise
performance of the device.
2 Represents the cycle-to-cycle residual jitter from the comparator alone.
3 Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
4 The maximum frequency of the serial I/O port refers to the maximum speed of the port during a write operation. During a register readback, the maximum port speed
is restricted to 2 Mbps.
5 Setup time refers to the TCSU (setup time of the falling edge of CS to the SCLK rising edge) and TDSU (setup time of the data change on SDIO to the SCLK rising edge).
6 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions section). The longest time required is for the reference clock
multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used.
7 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
8 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates 50 MHz, the high speed sync enable bit, CFR2 [11], should be set.
9 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
Rev. B | Page 5 of 28

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