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ADC-207MM 데이터시트 PDF




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부품번호 ADC-207MM 기능
기능 7- BIT 20MHZ CMOS FLASH A/D CONVERTERS
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ADC-207MM 데이터시트, 핀배열, 회로
®®
INN O VAT IO N a n d E X C E L L E N C E
ADC-207
7-Bit, 20MHz, CMOS
Flash A/D Converters
FEATURES
7-bit flash A/D converter
20MHz sampling rate
Low power (250mW)
Single +5V supply
1.2 micron CMOS technology
7-bit latched 3-state output with overflow bit
Surface-mount versions
High-reliability version
No missing codes
GENERAL DESCRIPTION
The ADC-207 is the industry’s first 7-bit flash converter using an
advanced high-speed VLSI 1.2 micron CMOS process. This
process offers some very distinctive advantages over other
processes, making the ADC-207 unique. The smaller
geometrics of the process achieve high speed, better linearity
and superior temperature performance.
Since the ADC-207 is a CMOS device, it also has very low
power consumption (250mW). The device draws power from
a single +5V supply and is conservatively rated for 20MHz
operation. The ADC-207 allows using sampling apertures as
small as 12ns, making it more closely approach an ideal
sampler. The small sampling apertures also let the device
operate at greater than 20MHz.
The ADC-207 has 128 comparators which are auto-balanced
on every conversion to cancel out any offsets due to
temperature and/or dynamic effects. The resistor ladder has a
midpoint tap for use with an external voltage source to improve
integral linearity beyond 7 bits. The ADC-207 also provides the
user with 3-state outputs for easy interfacing to other
components.
There are six models of the ADC-207 covering two operating
temperature ranges, 0 to +70°C and –55 to +125°C. Two high-
reliability "QL" models are also available.
ANALOG INPUT 4
+REFERENCE 6
R/2
+VDD
+5V SUPPLY 18
R
DIGITAL GROUND 2
ANALOG GROUND 7
R
RANGE MIDPOINT 5
R/2
R/2
2
1
R
–REFERENCE 3
R
CS1 8
CS2 9
D
GQ
D
GQ
128-TO-7
ENCODER
D
GQ
D
GQ
D
GQ
2
1
CLOCK
GENERATOR
1 CLOCK INPUT
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
10 OVERFLOW
11 BIT 1 (MSB)
12 BIT 2
13 BIT 3
14 BIT 4
15 BIT 5
16 BIT 6
17 BIT 7 (LSB)
INPUT/OUTPUT
CONNECTIONS
DIP
PINS
FUNCTION
LCC
PINS
1 CLOCK INPUT
2 DIGITAL GROUND
3 –REFERENCE
4 ANALOG INPUT
5 MIDPOINT
6 +REFERENCE
7 ANALOG GROUND
8 CS1
9 CS2
10 OVERFLOW
11 BIT 1 (MSB)
12 BIT 2
13 BIT 3
14 BIT 4
15 BIT 5
16 BIT 6
17 BIT 7 (LSB)
18 +5V SUPPLY
1
4
5
6
7
8
9
11
12
13
14
16
17
19
20
21
23
24
Figure 1. ADC-207 Functional Block Diagram (DIP Pinout)
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) Tel: (508) 339-3000 Fax: (508) 339-6356 For immediate assistance (800) 233-2765




ADC-207MM pdf, 반도체, 판매, 대치품
ADC-207
CLOCK IN
GROUND
+5 VOLTS
9
0.01µF
4
5
8
6 20k
1
2
10pF
®®
13
11
12 CLOCK OUT
3
to 12ns to improve performance above
20MHz. Such a configuration will closely
resemble an ideal sampler.
Figure 3. Optional Pulse Shaping Circuit
USING TWO ADC-207’S FOR 8-BIT RESOLUTION
Two ADC-207’s (A and B) are cascadable for applications
requiring 8-bit resolution. The device A provides a typical 7-bit
output. The OVERFLOW signal of device A turns off device A
and turns on the device B. The OVERFLOW signal of device A
is also used as MSB for 8-bit operation. The device B provides
the other seven bits from the input signal. Figure 4 shows the
circuit connections for the application.
+5V
+5.12
REFERENCE
IN
10
TURN
OPTIONAL
MIDSCALE
ADJUST
CLOCK IN
18
6 +VDD
+REFERENCE
8
CS1
4
ANALOG INPUT
1
CLOCK
9
CS2
3
–REFERENCE
OF
B1
B2
B3
B4
B5
B6
B7
DIG GND
10
11
12
13
14
15
16
17
2
ANALOG GROUND
7
ANALOG IN
+5V
7
ANALOG GROUND
6 +REFERENCE
8
CS1
1 CLOCK
4 ANALOG INPUT
OF
B1
B2
B3
B4
9 CS2
B5
18 +VDD
3 –REFERENCE
B6
B7
DIG GND
10
11
12
13
14
15
16
17
2
OVERFLOW
BIT 1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8 (LSB)
BEAT FREQUENCY AND ENVELOPE TESTS
Figure 5 shows an actual ADC-207 plot of the Beat Frequency
Test. This test uses a 20MHz clock input to the ADC-207 with
a 20.002MHz full-scale sine wave input. Although the
converter would not normally be used in this mode because
the input frequency violates Nyquist criteria for full recovery of
signal information, the test is an excellent demonstration of the
ADC-207’s high-frequency performance.
The effect of the 2kHz frequency difference between the input
and the clock is that the output will be a 2kHz sinusoidal digital
data array which "walks" along the actual input at the 2kHz
beat note frequency. Any inability to follow the 20.002MHz
input will be immediately obvious by plotting the digital data
array. Further arithmetic analysis may be done on the data
array to determine spectral purity, harmonic distortion, etc.
This test is an excellent indication of:
1. Full power input bandwidth of all 128 comparators.
(Any gain loss would show as signal distortion.)
2. Phase response linearity vs. instantaneous signal
magnitude. (Phase problems would show as
improper codes.)
3. Comparator slew rate limiting.
Figure 6 shows an actual ADC-207 plot of the Envelope Test.
This test is a variation of the previous test but uses a
10.002MHz sinewave input to give two overlapping cycles
when the data is reconstructed by a D/A converter output to an
oscilloscope. The scope is triggered by the 20MHz clock used
by the A/D. Any asymmetry between positive and negative
portions of the signal will be very obvious. This test is an
excellent indication of slew rate capability. At the peaks of the
envelope, consecutive samples swing completely through the
input voltage range.
REFERENCE
GROUND
NOTE: The output data bit numbering is offset
by a bit to the device B’s output.
Figure 4. Using Two ADC-207’s for 8-Bit Operation

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