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ADC-318A 데이터시트 PDF




ETC에서 제조한 전자 부품 ADC-318A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ADC-318A 기능
기능 8-Bit/ 120MHz and 140MHz Full-Flash A/D Converter
제조업체 ETC
로고 ETC 로고


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ADC-318A 데이터시트, 핀배열, 회로
®®
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz
Full-Flash A/D Converter
FEATURES
Low power dissipation (960mW max.)
TTL compatible output
Diff./Integral nonlinearity (±½LSB max.)
1:2 Demultiplexed straight output programmable
2:1 Frequency divided TTL clock output with reset
Surface mount package
Selectable Input Logic (TTl, ECL, PECL)
+5V or ±5V Power Supply Operation
GENERAL DESCRIPTION
The ADC-318 and ADC-318A are 8 bit monolithic bipolar,
full flash A/D converters. Though they have high, 120MHz
(ADC-318) and 140MHz (ADC-318A), sampling rates, their
input logic level, including the start convert pulse, is TTL,
ECL and PECL compatible. Digital outputs are also TTL
compatible and allow a straight output or a programmable
1:2 de-multiplexed output.
The ADC-318 and ADC-318A feature ±1/2 LSB max.
integral and differential non-linearity, +5V single or ±5V dual
power supply operation, a low 960mW maximum power
dissipation, 150MHz wide analog input range and excellent
temperature coefficient in a small 48 pin QFP package. The
start convert pulse can have a 50% duty cycle.
The ADC-318 and ADC-318A offer low cost, easy to use
functionality for design engineers.
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION
PIN FUNCTION
1 –DVs (Digital)
48
2 REF. BOTTOM (VRB)
47
3 ANALOG GROUND
46
4 REF. MID POINT (VRM1) 45
5 +AVS (Analog)
44
6 ANALOG IN (VIN)
43
7 REF. MID POINT (VRM2) 42
8 +AVS (Analog)
41
9 REF. MID POINT (VRM3) 40
10 ANALOG GROUND
39
11 REF. TOP (VRT)
38
12 DIGITAL GROUND 3
37
13 A/D CLOCK ECL/PECL 36
14 A/D CLOCK ECL/PECL 35
15 A/D CLOCK TTL
34
16 NO CONNECTION
33
17 NO CONNECTION
32
18 NO CONNECTION
31
19 +DVS2 (Digital)
30
20 DIGITAL GROUND 2
29
21 B BIT 8 (LSB)
28
22 B BIT 7
27
23 B BIT 6
26
24 B BIT 5
25
RSET ECL/PECL
RSET ECL/PECL
RSET TTL
SELECT
INV
TTL CLOCK OUT
+DVS2 (Digital)
DIGITAL GROUND 2
A BIT 1 (MSB)
A BIT 2
A BIT 3
A BIT 4
A BIT 5
A BIT 6
A BIT 7
A BIT 8 (LSB)
DIGITAL GROUND 2
+DVS2 (Digital)
+DVS1 (Digital)
DIGITAL GROUND 1
B BIT 1 (MSB)
B BIT 2
B BIT 3
B BIT 4
VIN 6
VRT 11
VRM3 9
VRM2 7
VRM1 4
VRB 2
A/D CLOCK ECL/PECL 13
A/D CLOCK ECL/PECL 14
A/D CLOCK TTL 15
RSET ECL/PECL 48
RSET ECL/PECL 47
RSET TTL 46
6
6
256
6
6
DELAY
DQ
Q
8
A
LATCH
8
A
TTL
OUTPUT
44 INV
33 BIT 8 (LSB)
34 BIT 7
35 BIT 6
36 BIT 5 A OUTPUT
37 BIT 4
38 BIT 3
39 BIT 2
40 BIT 1 (MSB)
B
LATCH
6
B
TTL
OUTPUT
21 BIT 8 (LSB)
22 BIT 7
23 BIT 6
24 BIT 5 B OUTPUT
25 BIT 4
26 BIT 3
27 BIT 2
28 BIT 1 (MSB)
SELECT
43 CLOCK OUT
TTL
45 SELECT
Figure 1. ADC-318/318A Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) Tel: (508) 339-3000, (800)233-2765 Fax: (508) 339-6356 Email: [email protected] Internet: www.datel.com




ADC-318A pdf, 반도체, 판매, 대치품
ADC-318, ADC-318A
®®
the reference input voltages given to VRT and VRB. Keep
the ranges of V within values shown in this data sheet.
Standard settings are VRT = +4.0V, V input range from
+2 to +4V. This setting can be varied to VRT = +3.5V,
VRB = +2V and 1.5V p-p analog input range, depending
on your selection of amplifiers which may provide less
than +4V output.
5. The ADC-318 and ADC-318A have resistor matrix taps at
VRM1 (pin 4), VRM2 (pin 7) and VRM3 (pin 9). These pins
provide ¼, ½ and ¾ full scale of VRT-VRB voltage respec-
tively. These outputs may be used to adjust the integral
non-linearity. Bypass these pins to GND with 0.1uF ceramic
chip capacitors.
6. A/D CLK input and RSET/RSET inputs are TTL or ECL,
PECL (Positive ECL) compatible. Pins are provided
individually. TTL or PECL is available with +5V single power
applied. ECL is available with ±5V dual power applied. The
connections of –DVs (pin 1) and DGND3 (pin12) are
different depending on the power supply mode used. Refer
to Figures 2-1 and 2-2.
a. For +5V single power (TTL or PECL) –DVs (pin 1) is
connected to DGND. DGND3 (pin 12) is connected
to +5V power.
b. For ±5V dual power (ECL) –DVs (pin 1) is connected
to –5V power. DGND3 (pin 12) is connected to DGND.
7. When the A/D CLK is driven with ECL or PECL, A/D CLK
(pin 13) and A/D CLK (pin 14) are to be driven by differen-
tial logic inputs to avoid unstable performance at critically
high speeds. If a risk of unstable performance is accept-
able, single logic input can be used opening A/D CLK (pin
14). The A/D CLK pin should be bypassed to DGND with a
0.1uF ceramic capacitor. When connected this way there
will be a voltage of DGND –1.2V on the A/D CLK pin. This
voltage can not be used as a threshold voltage for ECL or
PECL. Input the A/D CLK pulse to pin 15 when TTL is
selected.
8. The ADC-318 and ADC-318A have RSET/RSET input pins.
An internal frequency half divider can be initialized with
inputs to these pins. With ECL or PECL, differential inputs
are given to RSET (pin 48) and RSET (pin 47). This
function can be achieved with a single input, leaving pin 47
open and bypassing to DGND with a 0.1uF ceramic chip
capacitor. The voltage level of pin 47 is the threshold
voltage of ECL or PECL. Use RSET (pin 46) for TTL.
9. SELECT (pin 45) is used to set output mode. Connection of
this pin to DGND selects the straight output mode and
connection to +DVs selects the 1:2 de-multiplexed output
mode. The maximum sampling rates are 100MHz for straight
mode (For both models, ADC-318 and ADC-318A) and
120MHz (ADC-318) and 140MHz (ADC-318A) for de-
multiplexed mode. Refer to figure 2-4. There is an applica-
tion where a multiple number of ADC-318/318A's are used
with a common A/D CLK and outputs are in de-multiplexed
mode. In this case, the initial conditions of the frequency half
divider of each A/D Converter are not synchronized and it is
possible that each converter may have one clock maximum
of timing lag. This lag can be avoided by giving a common
RSET pulse to all converters at power ON. (See Figure 3-3
and 3-4, timing diagrams.)
10.The ADC-318 and ADC-318A have a TTL compatible CLK
OUT (pin 43). Since the rising edge of this pulse can provide
Setup and Hold time of output data, regardless of the output
mode, this signal can be used as synchronization pulse for
external circuits. Data output timing is different for the
straight mode and the de-multiplexed mode. See the timing
chart Figure 3.
11. INV (pin 44) is used to invert polarity of the TTL compatible
output data from both A and B ports. Leaving this pin open
or connected to +DVs makes the output positive true and
connection to DGND makes it negative true logic. See
input/output code table, Table 4.
Table 3: Logic Input Level vs. Power Supply Settings
DIGITAL INPUT
LEVEL
–DVS
DGND3
SUPPLY
VOLTAGES
TTL
PECL
ECL
0V +5V
0V +5V
–5V 0V
+5V
+5V
±5V
Table 4: Digital Output Coding
SIGNAL
INPUT
VOLTAGE
VRT
VRM2
VRB
DIGITAL OUTPUT CODE (A,B OUTPUT)
INV=1
INV=0
LSB
MSB LSB
MSB
11111111
00000000
10000000
01111111
01111111
10000000
00000000
11111111
11
ADC-318
ADC-318A
12
13 14 15 16 17 18
TTL LEVEL CLOCK INPUT
A/D CLOCK
A/D CLOCK
A/D CLOCK
ECL, PECL LEVEL CLOCK INPUTS
Figure 2-3: A/D Clock Input Connection
TTL LEVEL RESET INPUT
RSET
RSET
RSET
ECL, PECL LEVEL
RESET INPUTS
5V(D)
A/D CONVERSION MODE
DEMULTIPLEXED DATA OUT
STRAIGHT DATA OUT
5V(D)
OUTPUT CODING
STRAIGHT BINARY
COMPLEMENTARY BINARY
48 47 46 45 44 43 42
1 ADC-318
ADC-318A
2
TTL CLOCK OUT
Figure 2-4: Digital Input/Output Connections
4

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ADC-318A 전자부품, 판매, 대치품
®®
ADC-318, ADC-318A
Figure 5: Evaluation Circuit Diagram
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
ADC-318

8-Bit/ 120MHz and 140MHz Full-Flash A/D Converter

ETC
ETC
ADC-318A

8-Bit/ 120MHz and 140MHz Full-Flash A/D Converter

ETC
ETC

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