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ADC0803 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 ADC0803은 전자 산업 및 응용 분야에서
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부품번호 ADC0803 기능
기능 8-Bit/ Microprocessor-Compatible/ A/D Converters
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ADC0803 데이터시트, 핀배열, 회로
®
Data Sheet
ADC0803, ADC0804
August 2002
FN3094.4
8-Bit, Microprocessor-Compatible, A/D
Converters
The ADC080X family are CMOS 8-Bit, successive-
approximation A/D converters which use a modified
potentiometric ladder and are designed to operate with the
8080A control bus via three-state outputs. These converters
appear to the processor as memory locations or I/O ports,
and hence no interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Typical Application Schematic
ANY
µPROCESSOR
1 CS
2 RD
V+ 20 +5V 150pF
CLK R 19
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
6
7
8
DIFF
INPUTS
VREF/2 9 VREF/2
DGND 10
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
Features
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . <100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• Analog Voltage Input Range
(Single + 5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0V to 5V
• No Zero-Adjust Required
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
Pinout
ADC0803, ADC0804
(PDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
Ordering Information
PART NUMBER
ADC0803LCN
ADC0804LCN
ERROR
±1/2 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
0 to 70
20 Ld PDIP
PKG. NO
E20.3
E20.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved




ADC0803 pdf, 반도체, 판매, 대치품
ADC0803, ADC0804
Electrical Specifications (Notes 2, 8) (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX, Unless Otherwise Specified
CONTROL INPUTS (Note 7)
Logic “1“ Input Voltage (Except Pin 4 CLK V+ = 5.25V
IN), VINH
Logic “0“ Input Voltage (Except Pin 4 CLK V+ = 4.75V
IN), VINL
CLK IN (Pin 4) Positive Going Threshold
Voltage, V+CLK
CLK IN (Pin 4) Negative Going Threshold
Voltage, V-CLK
CLK IN (Pin 4) Hysteresis, VH
Logic “1” Input Current (All Inputs), IINHI VlN = 5V
Logic “0” Input Current (All Inputs), IINLO VlN = 0V
Supply Current (Includes Ladder Current), I+ fCLK = 640kHz, TA = 25oC and CS = Hl
DATA OUTPUTS AND INTR
2.0 - V+
- - 0.8
2.7 3.1 3.5
1.5 1.8 2.1
0.6 1.3 2.0
- 0.005 1
-1 -0.005
-
- 1.3 2.5
V
V
V
V
V
µΑ
µA
mA
Logic “0” Output Voltage, VOL
lO = 1.6mA, V+ = 4.75V
-
- 0.4
V
Logic “1” Output Voltage, VOH
lO = -360µA, V+ = 4.75V
2.4 -
-
V
Three-State Disabled Output Leakage (All
Data Buffers), ILO
Output Short Circuit Current, ISOURCE
Output Short Circuit Current, ISINK
VOUT = 0V
VOUT = 5V
VOUT Short to GND, TA = 25oC
VOUT Short to V+, TA = 25oC
-3 - - µA
- - 3 µA
4.5 6 - mA
9.0 16 - mA
NOTES:
2. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the DGND,
being careful to avoid ground loops.
3. For VIN(-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will
forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing
at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause
errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than 50mV, the output code will
be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature
variations, initial tolerance and loading.
4. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
5. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process.
6. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse width will
hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).
7. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
8. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span exists
(for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet.
Timing Waveforms
V+
RD
CS
DATA
OUTPUT
CL 10K
FIGURE 1A. t1H
2.4V
RD
0.8V
tr = 20ns
tr
90%
50%
10%
VOH
DATA
OUTPUTS
GND
t1H
90%
FIGURE 1B. t1H, CL = 10pF
4

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ADC0803 전자부품, 판매, 대치품
ADC0803, ADC0804
Timing Diagrams (Continued)
INTR
INTR RESET
CS tRI
RD
DATA
OUTPUTS
VALID
DATA
tACC
THREE-STATE
(HI-Z)
t1H , t0H
VALID
DATA
FIGURE 10B. OUTPUT ENABLE AND RESET INTR
D+1
D
D-1
56
34
12
+1 LSB
+1/2 LSB
0
-1/2 LSB
135
* QUANTIZATION ERROR
2 46
A-1
A A+1
ANALOG INPUT (VIN)
-1 LSB
A-1 A A+1
ANALOG INPUT (VIN)
TRANSFER FUNCTION
FIGURE 11A. ACCURACY = ±0 LSB; PERFECT A/D
ERROR PLOT
D+1
D
D-1
5
6
3
4
1
2
A-1
A A+1
ANALOG INPUT (VIN)
+1 LSB
0
-1 LSB
1
3 6 * QUANTIZATION
ERROR
A-1
4
2
A A+1
ANALOG INPUT (VIN)
TRANSFER FUNCTION
ERROR PLOT
FIGURE 11B. ACCURACY = ±1/2 LSB
FIGURE 11. CLARIFYING THE ERROR SPECS OF AN A/D CONVERTER
7

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