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ADC0804 데이터시트 PDF




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부품번호 ADC0804 기능
기능 8-Bit uP Compatible A/D Converters
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ADC0804 데이터시트, 핀배열, 회로
November 1999
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit µP Compatible A/D Converters
General Description
The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation A/D
converters that use a differential potentiometric
ladder — similar to the 256R products. These converters are
designed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE® output latches di-
rectly driving the data bus. These A/Ds appear like memory
locations or I/O ports to the microprocessor and no interfac-
ing logic is needed.
Differential analog voltage inputs allow increasing the
common-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Features
n Compatible with 8080 µP derivatives — no interfacing
logic needed - access time - 135 ns
n Easy interface to all microprocessors, or operates “stand
alone”
n Differential analog voltage inputs
n Logic inputs and outputs meet both MOS and TTL
voltage level specifications
n Works with 2.5V (LM336) voltage reference
n On-chip clock generator
n 0V to 5V analog input voltage range with single 5V
supply
n No zero adjust required
n 0.3" standard width 20-pin DIP package
n 20-pin molded chip carrier or small outline package
n Operates ratiometrically or with 5 VDC, 2.5 VDC, or
analog span adjusted voltage reference
Key Specifications
n Resolution
n Total error
n Conversion time
8 bits
±14 LSB, ±12 LSB and ±1 LSB
100 µs
Connection Diagram
ADC080X
Dual-In-Line and Small Outline (SO) Packages
Ordering Information
TEMP RANGE
±14 Bit Adjusted
ERROR
±12 Bit Unadjusted
±12 Bit Adjusted
±1Bit Unadjusted
PACKAGE OUTLINE
DS005671-30
See Ordering Information
0˚C TO 70˚C
ADC0802LCWM
ADC0804LCWM
M20B — Small
Outline
0˚C TO 70˚C
−40˚C TO +85˚C
ADC0801LCN
ADC0802LCN
ADC0803LCN
ADC0804LCN
ADC0805LCN/ADC0804LCJ
N20A — Molded DIP
TRI-STATE® is a registered trademark of National Semiconductor Corp.
Z-80® is a registered trademark of Zilog Corp.
© 1999 National Semiconductor Corporation DS005671
www.national.com




ADC0804 pdf, 반도체, 판매, 대치품
AC Electrical Characteristics (Continued)
The following specifications apply for VCC=5 VDC and TMINTATMAX unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max
COUT
TRI-STATE Output
Capacitance (Data Buffers)
5 7.5
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1)
Logical “1” Input Voltage
(Except Pin 4 CLK IN)
VCC=5.25 VDC
2.0 15
VIN (0)
Logical “0” Input Voltage
(Except Pin 4 CLK IN)
VCC=4.75 VDC
0.8
IIN (1)
Logical “1” Input Current
(All Inputs)
VIN=5 VDC
0.005
1
IIN (0)
Logical “0” Input Current
(All Inputs)
VIN=0 VDC
−1 −0.005
CLOCK IN AND CLOCK R
VT+ CLK IN (Pin 4) Positive Going
Threshold Voltage
2.7 3.1 3.5
VT− CLK IN (Pin 4) Negative
Going Threshold Voltage
1.5 1.8 2.1
VH
VOUT (0)
CLK IN (Pin 4) Hysteresis
(VT+)−(VT−)
Logical “0” CLK R Output
Voltage
VOUT (1)
Logical “1” CLK R Output
Voltage
DATA OUTPUTS AND INTR
IO=360 µA
VCC=4.75 VDC
IO=−360 µA
VCC=4.75 VDC
0.6 1.3 2.0
0.4
2.4
VOUT (0)
Logical “0” Output Voltage
Data Outputs
INTR Output
VOUT (1)
VOUT (1)
IOUT
Logical “1” Output Voltage
Logical “1” Output Voltage
TRI-STATE Disabled Output
Leakage (All Data Buffers)
ISOURCE
ISINK
POWER SUPPLY
IOUT=1.6 mA, VCC=4.75 VDC
0.4
IOUT=1.0 mA, VCC=4.75 VDC
0.4
IO=−360 µA, VCC=4.75 VDC
2.4
IO=−10 µA, VCC=4.75 VDC
4.5
VOUT=0 VDC
−3
VOUT=5 VDC
3
VOUT Short to Gnd, TA=25˚C
4.5
6
VOUT Short to VCC, TA=25˚C
9.0
16
ICC Supply Current (Includes
Ladder Current)
fCLK=640 kHz,
VREF/2=NC, TA=25˚C
and CS =5V
ADC0801/02/03/04LCJ/05
1.1 1.8
ADC0804LCN/LCWM
1.9 2.5
Units
pF
VDC
VDC
µADC
µADC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
µADC
µADC
mADC
mADC
mA
mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.
Note 4: For VIN(−)VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct
for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high
level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct.
To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance
and loading.
Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex-
tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 4 and section 2.0.
www.national.com
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ADC0804 전자부품, 판매, 대치품
Timing Diagrams (All timing is measured from the 50% voltage points) (Continued)
Output Enable and Reset with INTR
Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR .
Typical Applications
DS005671-52
6800 Interface
Ratiometeric with Full-Scale Adjust
DS005671-53
Note: before using caps at VIN or VREF/2,
see section 2.3.2 Input Bypass Capacitors.
DS005671-54
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