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ADC08062 데이터시트 PDF




National Semiconductor에서 제조한 전자 부품 ADC08062은 전자 산업 및 응용 분야에서
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부품번호 ADC08062 기능
기능 500 ns A/D Converter with S/H Function and Input Multiplexer
제조업체 National Semiconductor
로고 National Semiconductor 로고


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ADC08062 데이터시트, 핀배열, 회로
June 1999
ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input
Multiplexer
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a
two-channel multiplexer. The ADC08061/2 family performs
an 8-bit conversion using a 2-bit voltage estimator that gen-
erates the 2 MSBs and two low-resolution (3-bit) flashes that
generate the 6 LSBs.
Input track-and-hold circuitry eliminates the need for an ex-
ternal sample-and-hold. The ADC08061/2 family performs
accurate conversions of full-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
without need of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows the parts to be I/O or memory
mapped.
Key Specifications
n Resolution
n Conversion Time
n Full Power Bandwidth
n Throughput rate
n Power Dissipation
n Total Unadjusted Error
8 bits
560 ns max (WR-RD Mode)
300 kHz
1.5 MHz
100 mW max
±12 LSB and ±1 LSB
Features
n 1 or 2 input channels
n No external clock required
n Analog input voltage range from GND to V+
n Overflow output available for cascading (ADC08061)
n ADC08061 pin-compatible with the industry standard
ADC0820
Applications
n Mobile telecommunications
n Hard disk drives
n Instrumentation
n High-speed data acquisition systems
Block Diagram
* ADC08061
** ADC08062
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011086
DS011086-1
www.national.com




ADC08062 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+)
Logic Control Inputs
Voltage at Other lInputs and Outputs
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
J Package
N Package
WM Package
Storage Temperature
6V
−0.3V to V+ + 0.3V
−0.3V to V+ + 0.3V
5 mA
20 mA
875 mW
875 mW
875 mW
−65˚C to +150˚C
Lead Temperature (Note 5)
J Package (Soldering, 10 sec.)
N Package (Soldering, 10 sec.)
WM Package
(Vapor Phase, 60 sec.)
WM Package (Infrared, 15 sec.)
ESD Susceptibility (Note 6)
+300˚C
+260˚C
+215˚C
+220˚C
2 kV
Operating Ratings (Notes 1, 2)
Temperature Range
ADC08061/2BIN,
ADC08061/2CIWM
Supply Voltage, (V+)
TMIN TA TMAX
−40˚C TA 85˚C
4.5V to 5.5V
Converter Characteristics
The
face
following specifications
limits apply for TA =
apply for RD
TJ = TMIN to
Mode,
TMAX;
aVll+o=th5eVr ,limVRitsEFT+A==5TVJ,
a=n2d5V˚CR.EF−
=
GND
unless
otherwise
specified.
Bold-
Symbol
Parameter
Conditions
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
INL
Integral Non Linearity
ADC08061/2BIN
±12 LSB (max)
ADC08061/2CIWM
±1 LSB (max)
TUE
Total Unadjusted Error
ADC08061/2BIN
±12 LSB (max)
ADC08061/2CIWM
±1 LSB (max)
Missing Codes
0 Bits (max)
Reference Input Resistance
700 500 (min)
700
1250
(max)
VREF+
Positive Reference
Input Voltage
VREF−
V+
V (min)
V (max)
VREF−
VIN
Negative Reference
Input Voltage
Analog
Input Voltage
(Note 10)
GND
VREF+
GND − 0.1
V+ + 0.1
V (min)
V (max)
V (min)
V (max)
On Channel Input
On Channel Input = 5V,
−0.4
−20 µA (max)
Current
Off Channel Input = 0V (Note 11)
On Channel Input = 0V,
−0.4
−20 µA (max)
Off Channel Input = 5V (Note 11)
PSS
Power Supply Sensitivity
V+ = 5V ±5%, VREF = 4.75V
All Codes Tested
±1/16
±12 LSB (max)
Effective Bits
7.8 Bits
Full-Power Bandwidth
300 kHz
THD
Total Harmonic Distortion
0.5 %
S/N Signal-to-Noise Ratio
50 dB
IMD Intermodulation Distortion
50 dB
AC Electrical Characteristics
The following specifications apply for V+ = 5V, tr = tf = 10 ns, VREF+ = 5V, VREF− = 0V unless otherwise specified. Bold-
face limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Condition
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
tWR Write Time
Mode Pin to V+;
100 100 ns (min)
(Figures 2, 3, 4)
tRD
Read Time (Time from Falling Edge
Mode Pin to V+; (Figure 2)
350
350 ns (min)
of WR to Falling Edge of RD )
www.national.com
4

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ADC08062 전자부품, 판매, 대치품
DC Electrical Characteristics (Continued)
Note 8: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V+ and the other is connected to
GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V+ or below GND. Therefore,
caution should be exercised when testing with V+ = 4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated tem-
peratures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output code will
be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel will corrupt
the reading of a selected channel. An absolute analog input signal voltage range of 0V VIN 5V can be achieved by ensuring that the minimum supply voltage ap-
plied to V+ is 4.950V over temperature variations, initial tolerance, and loading.
Note 11: Off-channel leakage current is measured after the on-channel selection.
TRI-STATE Test Circuits and Waveforms
t1H
t1H, CL = 10 pF
DS011086-2
tr = 10 ns
DS011086-4
t0H t0H, CL = 10 pF
DS011086-3
tr = 10 ns
DS011086-5
7 www.national.com

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