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ADC0808 데이터시트 PDF




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부품번호 ADC0808 기능
기능 8-Bit uP Compatible A/D Converters with 8-Channel Multiplexer
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ADC0808 데이터시트, 핀배열, 회로
ADC0808/ADC0809
July 8, 2009
8-Bit μP Compatible A/D Converters with 8-Channel
Multiplexer
General Description
The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital con-
verter, 8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive ap-
proximation as the conversion technique. The converter fea-
tures a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive
approximation register. The 8-channel multiplexer can direct-
ly access any of 8-single-ended analog signals.
The device eliminates the need for external zero and full-scale
adjustments. Easy interfacing to microprocessors is provided
by the latched and decoded multiplexer address inputs and
latched TTL TRI-STATE outputs.
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, ex-
cellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally suit-
ed to applications from process and machine control to con-
sumer and automotive applications. For 16-channel multi-
plexer with common output (sample/hold port) see ADC0816
data sheet. (See AN-247 for more information.)
Features
Easy interface to all microprocessors
Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to VCC input range
Outputs meet TTL voltage level specifications
ADC0808 equivalent to MM74C949
ADC0809 equivalent to MM74C949-1
Key Specifications
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
8 Bits
±½ LSB and ±1 LSB
5 VDC
15 mW
100 μs
Block Diagram
See Ordering Information
© 2009 National Semiconductor Corporation 5672
567201
www.national.com




ADC0808 pdf, 반도체, 판매, 대치품
Symbol
Parameter
Conditions
IIN(1)
Logical “1” Input Current (The Control
Inputs)
VIN=15V
IIN(0)
Logical “0” Input Current (The Control
Inputs)
VIN=0
ICC Supply Current
DATA OUTPUTS AND EOC (INTERRUPT)
fCLK=640 kHz
VOUT(1)
VOUT(0)
VOUT(0)
IOUT
Logical “1” Output Voltage
Logical “0” Output Voltage
Logical “0” Output Voltage EOC
TRI-STATE Output Current
VCC = 4.75V
IOUT = −360µA
IOUT = −10µA
IO=1.6 mA
IO=1.2 mA
VO=5V
VO=0
Min Typ Max Units
1.0 μA
−1.0
0.3 3.0
μA
mA
2.4 V
4.5 V
0.45 V
0.45 V
3 μA
−3 μA
Electrical Characteristics – Timing Specifications
Timing Specifications VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
MIn Typ
tSTCLK
tWS
tWALE
ts
tH
Start Time Delay from Clock
Minimum Start Pulse Width
Minimum ALE Pulse Width
Minimum Address Set-Up Time
Minimum Address Hold Time
(Figure 5)
(Figure 5)
(Figure 5)
(Figure 5)
(Figure 5)
300
100
100
25
25
tD
tH1, tH0
t1H, t0H
tc
fc
Analog MUX Delay Time From ALE RS=0Ω (Figure 5)
OE Control to Q Logic State
CL=50 pF, RL=10k (Figure 8)
OE Control to Hi-Z
CL=10 pF, RL=10k (Figure 8)
Conversion Time
fc=640 kHz, (Figure 5) (Note 7)
Clock Frequency
1
125
125
90 100
10 640
Max
900
200
200
50
50
2.5
250
250
116
1280
tEOC EOC Delay Time
(Figure 5)
0 8 + 2 μS
CIN
COUT
Input Capacitance
At Control Inputs
TRI-STATE Output Capacitance At TRI-STATE Outputs
10 15
10 15
Units
ns
ns
ns
ns
ns
μs
ns
ns
μs
kHz
Clock
Periods
pF
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage
of 4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust.
However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference
voltages can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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ADC0808 전자부품, 판매, 대치품
Timing Diagram
FIGURE 5.
567204
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