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ADC0808CCV 데이터시트 PDF




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부품번호 ADC0808CCV 기능
기능 P Compatible 8-Bit A/D Converter with 8-Channel Multiplexer
제조업체 Micro Linear Corporation
로고 Micro Linear Corporation 로고


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ADC0808CCV 데이터시트, 핀배열, 회로
May 1997
ML2258*
µP Compatible 8-Bit A/D Converter
with 8-Channel Multiplexer
GENERAL DESCRIPTION
The ML2258 combines an 8-bit A/D converter, 8-channel
analog multiplexer, and a microprocessor compatible 8-
bit parallel interface and control logic in a single
monolithic device.
Easy interface to microprocessors is provided by the
latched and decoded multiplexer address inputs and
latched three-state outputs.
The device is suitable for a wide range of applications
from process and machine control to consumer,
automotive, and telecommunication applications.
The ML2258 is an enhanced, pin-compatible, second
source for the industry standard ADC0808/ADC0809. The
ML2258 enhancements are faster conversion time, true
sample and hold function, superior power supply
rejection, wider reference range, and a double buffered
data bus as well as faster digital timing. All parameters
are guaranteed over temperature with a power supply
voltage of 5V ±10%.
BLOCK DIAGRAM
FEATURES
s Conversion time
6.6µs
s Total unadjusted error
±1/2LSB or ±1LSB
s No missing codes
s Sample and hold
390ns acquisition
s Capable of digitizing a 5V, 50kHz sine wave
s 8-input multiplexer
s 0V to 5V analog input range with single 5V
power supply
s Operates ratiometrically or with up to 5V
voltage reference
s No zero-or full-scale adjust required
s Analog input protection
25mA per input min
s Low power dissipation
3mA max
s TTL and CMOS compatible digital inputs and outputs
s Standard 28-pin DIP or surface mount PCC
s Superior pin compatible replacement for ADC0808 and
ADC0809
* Some Packages Are End Of Life As Of August 1, 2000
START CLOCK
IN0
IN1
IN2
IN3 8-CHANNEL
MULTIPLEXER
IN4
IN5
IN6
IN7
ADDR0
ADDR1
ADDR2
ADDRESS
LATCH ENABLE
ADDRESS
LATCH
AND
DECODER
A/D WITH
SAMPLE HOLD
CONTROL & TIMING
END OF CONVERSION
(INTERRUPT)
COMPARATOR
S.A.R.
SWITCH TREE
THREE
STATE
OUTPUT
LATCH
BUFFER
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VCC GND +VREF
CAPACITOR/
RESISTOR
ARRAY
–VREF OUTPUT
ENABLE
1




ADC0808CCV pdf, 반도체, 판매, 대치품
ML2258
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
NOTES
CONDITIONS
TYP
MIN (NOTE 4)
MAX
UNITS
AC and Dynamic Performance Characteristics (Note 10)
tACQ
fCLK
tC
SNR
Sample and Hold Acquisition
Clock Frequency
Conversion Time
Signal to Noise Ratio
THD Total Harmonic Distortion
5 100
5
VIN = 51kHz, 5V sine.
fCLK = 10.24MHz
(fSAMPLING > 150kHz). Noise is sum
of all nonfundamental components
up to 1/2 of fSAMPLING
VIN = 51kHz, 5V sine.
fCLK = 10.24MHz
(fSAMPLING > 150kHz). THD is sum
of 2, 3, 4, 5 harmonics relative to
fundamental
IMD Intermodulation Distortion
FR Frequency Response
VIN = fA + fB. fA = 49kHz, 2.5V sine.
fB = 47.8kHz, 2.5V sine,
fCLK = 10.24MHz
(fSAMPLING > 150kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental
VIN = 0 to 50kHz. 5V sine relative
to 1kHz
tDC
tEOC
tWS
tSS
tWALE
tS
tH
tH1, H0
t1H, 0H
CIN
COUT
Clock Duty Cycle
End of Conversion Delay
Start Pulse Width
Start Pulse Setup Time
Address Latch Enable Pulse Width
Address Setup
Address Hold
Output Enable for DB0–DB7
Output Disable for DB0–DB7
Capacitance of Logic Input
Capacitance of Logic Outputs
6, 11
5
5
6, 12
5
5
5
6
6
6
6
Synchronous only
Figure 1, CL = 50pF
Figure 1, CL = 10pF
Figure 1, CL = 50pF
Figure 1, CL = 10pF
40
50
40
50
0
50
4 1/fCLK
10240 kHz
67 67 + 250ns 1/fCLK
47 dB
–60 dB
–60 dB
0.1 dB
60 %
8 8 + 250ns 1/fCLK
ns
ns
ns
ns
ns
100 ns
50 ns
200 ns
100 ns
5 pF
10 pF
Note 1: Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with
respect to ground.
Note 2: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V– or VIN > V+) the absolute value of current at that pin should be limited to 25mA or less.
Note 3: –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-
case test conditions.
Note 4: Typicals are parametric norm at 25°C.
Note 5: Parameter guaranteed and 100% production tested.
Note 6: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 7: Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.
Note 8: For –VREF • VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages
one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can
cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either
diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an
absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: CL = 50pF, timing measured at 50% point.
Note 11: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,
the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs.
Note 12: The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,
start conversion will have an uncertainty of one clock pulse.
4

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ADC0808CCV 전자부품, 판매, 대치품
1.0 FUNCTIONAL DESCRIPTION
1.1 MULTIPLEXER ADDRESSING
The ML2258 contains an 8-channel single ended analog
multiplexer. A particular input channel is selected by using
the address decoder. The relationship between the address
inputs, ADDR0–ADDR2, and the analog input selected is
shown in Table 1. The address inputs are latched into the
decoder on the rising edge of the address latch signal ALE.
SELECTED
ANALOG CHANNEL
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
ADDRESS INPUT
ADDR2 ADDR1 ADDR0
000
001
010
011
100
101
110
111
Table 1. Multiplexer Address Decoding
1.2 A/D CONVERTER
The A/D converter uses successive approximation to
perform the conversion. The converter is composed of the
successive approximation register, the DAC and the
comparator.
The DAC generates the precise levels that determine the
linearity and accuracy of the conversion. The DAC is
composed of a capacitor upper array and a resistor lower
array. The capacitor upper array generates the 4 MSB
decision levels while the series resistor lower array generates
the 4 LSB decision levels. A switch decoder tree is used to
decode the proper level from both arrays.
ML2258
The capacitor/resistor array offers fast conversion, superior
linearity and accuracy since matching is only required
between 24 = 16 elements (as opposed to 28 = 256
elements in conventional designs). And since the levels are
based on the ratio of capacitors to capacitors and resistors to
resistors, the accuracy and long term stability of the
converter is improved. This also guarantees monotonicity
and no missing codes, as well as eliminating any linearity
temperature or power supply dependence.
The successive approximation register is a digital block used
to store the bit decisions from the conversion.
The comparator design is unique in that it is fully differential
and auto-zeroed. The fully differential architecture provides
excellent noise immunity, excellent power supply rejection,
and wide common mode range. The comparator is auto
zeroed at the start of each conversion in order to remove
any DC offset and full scale gain error, thus improving
accuracy and linearity.
Another advantage of the capacitor array approach used in
the ML2258 over conventional designs is the inherent
sample and hold function. This true S/H allows an accurate
conversion to be done on the input even if the analog signal
is not stable. Linearity and accuracy are maintained for
analog signals up to 1/2 the sampling frequency. As a result,
input signals up to 75kHz can be converted without
degradation in linearity or accuracy.
The sequence of events during a conversion is shown in
figure 5. The rising edge of a START pulse resets the internal
registers and the falling edge initiates a conversion on the
next rising edge of CLK. Four CLK pulses later, sampling of
the analog input begins. The input is then sampled for the
next four CLK periods until EOC goes low. EOC goes low on
the rising edge of the 8th CLK pulse indicating that the
conversion is now beginning. The actual conversion now
takes place for the next 56 CLK pulses, one bit for each 7
CLK pulses. After the conversion is done, the data is updated
on DB0–DB7 and EOC goes high on the rising edge of the
67th CLK pulse, indicating that the conversion has been
completed and data is valid on DB0–DB7. The data will stay
CLK
START
ALE
ADDR0–ADDR2
EOC
1/fCLK
1
tSS
2
tWS
tWALE
tS tH
DB0–DB7
OE
3
4
5
6
7
8
66
67 68
69
70
tEOC
tC
PREVIOUS DATA
Figure 5. Timing Diagram
DATA
tDIS
tH
tEN
7

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