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기능 8-Bit Serial I/O A/D Converter With 11-Channel Multiplexer
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ADC0811CCJ 데이터시트, 핀배열, 회로
December 1994
ADC0811 8-Bit Serial I O A D Converter
With 11-Channel Multiplexer
General Description
The ADC0811 is an 8-Bit successive approximation A D
converter with simultaneous serial I O The serial input con-
trols an analog multiplexer which selects from 11 input
channels or an internal half scale test voltage
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator This allows
the input signal to vary during the conversion cycle
Separate serial I O and conversion clock inputs are provid-
ed to facilitate the interface to various microprocessors
Features
Y Separate asynchronous converter clock and serial data
I O clock
Y 11-Channel multiplexer with 4-Bit serial address logic
Y Built-in sample and hold function
Y Ratiometric or absolute voltage referencing
Y No zero or full-scale adjust required
Y Internally addressable test voltage
Y 0V to 5V input range with single 5V power supply
Y TTL MOS input output compatible
Y 0 3 standard width 20-pin dip or 20-pin molded chip
carrier
Key Specifications
Y Resolution
Y Total unadjusted error
Y Single supply
Y Low Power
Y Conversion Time
8-Bits
g LSB and g 1LSB
5VDC
15 mW
32 mS
Connection Diagrams
Dual-In-Line Package
Functional Diagram
Top View
TL H 5587–1
Molded Chip Carrier (PCC) Package
Top View
TL H 5587–2
Order Number ADC0811J N V
See NS Packages J20A N20A V20A
Use Ordering Information
C1995 National Semiconductor Corporation TL H 5587
TL H 5587 – 3
RRD-B30M115 Printed in U S A




ADC0811CCJ pdf, 반도체, 판매, 대치품
Electrical Characteristics
The following specifications apply for VCC e 4 75V to 5 25V VREF e a4 6V to (VCC a 0 1V) w2 CLK e 2 097 MHz unless
otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C (Continued)
Parameter
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
AC CHARACTERISTICS (Continued)
tSDI Minimum DI Set-up Time to SCLK
Rising Edge
200
400
ns
tDDO Maximum Delay From SCLK
Falling Edge to DO Data Valid
tTRI Maximum DO Hold Time
(CS Rising edge to DO
TRI-STATE)
RLe30k
CLe100 pF
RLe3k
CLe100 pF
180 400
90 150
400
150
ns
ns
tCA Analog
Sampling Time
After Address Is Latched
CSeLow
4 SCLKa1 ms sec
tRDO Maximum DO
Rise Time
RLe30 kX ‘‘TRI-STATE’’ to ‘‘HIGH’’ State
CLe100 pf ‘‘LOW’’ to ‘‘HIGH’’ State
75
150
150
300
150
300
ns
tFDO Maximum DO
Fall Time
RLe30 kX ‘‘TRI-STATE’’ to ‘‘LOW’’ State
CLe100 pf ‘‘HIGH’’ to ‘‘LOW’’ State
75
150
150
300
150
300
ns
CIN Maximum Input
Capacitance
Analog Inputs ANO – AN10 and VREF
All Others
11
5
55 pF
15
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2 All voltages are measured with respect to ground
Note 3 Under over voltage conditions (VINk0V and VINlVCC) the maximum input current at any one pin is g5 mA If the voltage at more than one pin exceeds
VCC a 3V the total package current must be limited to 20 mA For example the maximum number of pins that can be over driven at the maximum current level of
g5 mA is four
Note 4 Total unadjusted error includes offset full-scale linearity multiplexer and hold step errors
Note 5 Two on-chip diodes are tied to each analog input which will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than VCC supply Be careful during testing at low VCC levels (4 5V) as high level analog inputs (5V) can cause this input diode to conduct especially at
elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to 5 VDC input voltage range will
therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading
Note 6 Typicals are at 25 C and represent most likely parametric norm
Note 7 Guaranteed and 100% production tested under worst case condition
Note 8 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels
Note 9 Channel leakage current is measured after the channel selection
Note 10 1 count e VREF 256
Note 11 Human body model 100 pF discharged through a 1 5 kX resistor
Test Circuits
Leakage Current
D0 Except ‘‘TRI-STATE’’
TL H 5587–17
4
TL H 5587 – 6

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ADC0811CCJ 전자부품, 판매, 대치품
Timing Diagrams (Continued)
CS High During Conversion
CS Low During Conversion
TL H 5587 – 4
TL H 5587 – 5
Note DO and DI lines share the 8-bit I O shift register(see Functional Block Diagram) Since the MUX address bits are shifted in on SCLK rising edges while SCLK
falling edges shift out conversion data on DO the eighth falling edge of SCLK will shift out the MSB MUX address bit (A7) on DO Thus if addressing channels
CH8–CH10 a high DO will occur momentarily (one w2 clock period) until the 8-bit I O shift register is cleared by the internal EOC signal
Channel Addressing Table
TABLE I ADC 0811 Channel Addressing
MUX ADDRESS
ANALOG CHANNEL
A7 A6 A5 A4 A3 A2 A1 A0
SELECTED
0 0 0 0XXXX
CH0
0 0 0 1XXXX
0 0 1 0XXXX
CH1
CH2
0 0 1 1XXXX
CH3
0 1 0 0XXXX
0 1 0 1XXXX
CH4
CH5
0 1 1 0XXXX
CH6
0 1 1 1XXXX
1 0 0 0XXXX
CH7
CH8
1 0 0 1XXXX
CH9
1 0 1 0XXXX
CH10
1 0 1 1XXXX
VTEST
1 1 X X X X X X LOGIC TEST MODE
Analog channel inputs CH0 thru CH3 are logic outputs
7

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