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ADC08161CIWM 데이터시트 PDF




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부품번호 ADC08161CIWM 기능
기능 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference
제조업체 National Semiconductor
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ADC08161CIWM 데이터시트, 핀배열, 회로
June 1999
ADC08161
500 ns A/D Converter with S/H Function and
2.5V Bandgap Reference
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08161 CMOS A/D converter offers 500 ns conver-
sion time, internal sample-and-hold (S/H), a 2.5V bandgap
reference, and dissipates only 100 mW of power. The
ADC08161 performs an 8-bit conversion with a 2-bit voltage
estimator that generates the 2 MSBs and two low-resolution
(3-bit) flashes that generate the 6 LBSs.
Input signals are tracked and held by the input sampling cir-
cuitry, eliminating the need for an external sample-and-hold.
The ADC08161 can perform accurate conversions of
full-scale input signals at frequencies from DC to typically
more than 300 kHz (full power bandwidth) without the need
of an external sample-and-hold (S/H).
For ease of interface to microprocessors, this part has been
designed to appear as a memory location or I/O port without
the need for external interfacing logic.
Key Specifications
n Resolution
n Conversion time (tCONV)
n Full power bandwidth
n Throughput rate
n Power dissipation
n Total unadjusted error
8 Bits
560 ns max (WR-RD Mode)
300 kHz (typ)
1.5 MHz min
100 mW max
±12 LSB and ±1 LSB max
Features
n No external clock required
n Analog input voltage range from GND to V+
n 2.5V bandgap reference
Applications
n Mobile telecommunications
n Hard-disk drives
n Instrumentation
n High-speed data acquisition systems
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011149
DS011149-1
www.national.com




ADC08161CIWM pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
The following specifications apply for V+ =
limits apply for TA = TJ = TMIN to TMAX;
5V, tr =
all other
tlfim=it1s0TnAs=, VTRJE=F+2=5˚C5V. ,
VREF−
=
0V
unless
otherwise
specified.
Boldface
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
tWR Write Time
Mode Pin to V+
(Figures 2, 3, 4)
100 100 ns (min)
tRD Read Time (Time from Rising Edge Mode Pin to V+, (Figure 2)
of WR to Falling Edge of RD )
350
350 ns (min)
tRDW
RD Width
Mode Pin to GND (Figure 5 )
200
400
250 ns (min)
400 ns (max)
tCONV
tCRD
tACCO
WR -RD Mode Conversion Time
(tWR + tRD + tACC1)
RD Mode Conversion Time
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode Pin to V+, (Figure 2 )
Mode Pin to GND, (Figure 1 )
CL 100 pF, Mode Pin to GND
(Figure 1 )
500
655
640
560 ns (max)
900 ns (max)
900 ns (max)
tACC1
Access Time (Delay from
Falling Edge of RD
to Output Valid)
CL 10 pF
CL = 100 pF
Mode Pin to V+, tRD tINTL
(Figure 2 )
45
50
ns
110 ns (max)
tACC2
Access Time (Delay from
Falling Edge of RD
to Output Valid)
CL 10 pF
CL = 100 pF
tRD > tINTL,
(Figures 3, 5)
25 ns
30 55 ns (max)
t1H, t0H
TRI-STATE® Control
(Delay from Rising Edge
RL = 3 k, CL = 10 pF
(Figures 1, 2, 3, 4, 5)
30 60 ns (max)
of RD to HI-Z State)
tINTL
Delay from Rising Edge of
WR to Falling Edge of INT
Mode Pin = V+, CL = 50 pF
(Figures 3, 4)
520
690 ns (max)
tINTH
Delay from Rising Edge of
RD to Rising Edge of INT
CL = 50 pF,
(Figures 1, 2, 3, 5)
50 95 ns (max)
tINTH
Delay from Rising Edge of
WR to Rising Edge of INT
CL = 50 pF, (Figure 4)
45 95 ns (max)
tRDY
tID
Delay from CS to RDY
Delay from INT
to Output Valid
Mode Pin = 0V, CL = 50 pF,
RL = 3 k, (Figure 1)
RL = 3 k, CL = 100 pF
(Figure 4)
25
0
45 ns (max)
15 ns (max)
tRI Delay from RD to INT
Mode Pin = V+, tRD tINTL
(Figure 2)
60
115 ns (max)
tN Time between End of RD
and Start of New Conversion
(Figures 1, 2, 3, 4, 5)
50 50 ns (min)
tCSS
tCSH
CS Setup Time
CS Hold Time
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
0 0 ns (max)
0 0 ns (max)
DC Electrical Characteristics
The following specifications apply
all other limits TA = TJ = 25˚C.
for
V+
=
5V
unless
otherwise
specified.
Boldface
limits
apply
for
TA
=
TJ
=
TMIN
to
TMAX;
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
VIH Logic “1” Input Voltage
V+ = 5.5 V
CS, WR, RD, A0, A1, A2 Pins
2.0 V (min)
Mode Pin
3.5
www.national.com
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ADC08161CIWM 전자부품, 판매, 대치품
TRI-STATE Test Circuit and Waveforms
t1H
t1H, CL = 10 pF
DS011149-2
DS011149-4
tr = 10 ns
t0H t0H, CL = 10 pF
DS011149-3
tr = 10 ns
DS011149-5
FIGURE 1. RD Mode (Mode Pin is Low)
DS011149-6
7 www.national.com

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부품번호상세설명 및 기능제조사
ADC08161CIWM

500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference

National Semiconductor
National Semiconductor

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