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PDF ADC78H90CIMTX Data sheet ( Hoja de datos )
| Número de pieza | ADC78H90CIMTX | |
| Descripción | 8-Channel/ 500 kSPS/ 12-Bit A/D Converter | |
| Fabricantes | National Semiconductor | |
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February 2004
ADC78H90
8-Channel, 500 kSPS, 12-Bit A/D Converter
General Description
The ADC78H90 is a low-power, eight-channel CMOS 12-bit
analog-to-digital converter with a conversion throughput of
500 kSPS. The converter is based on a successive-
approximation register architecture with an internal track-
and-hold circuit. It can be configured to accept up to eight
input signals at inputs AIN1 through AIN8.
The output serial data is straight binary, and is compatible
with several standards, such as SPI™, QSPI™, MICROW-
IRE™, and many common DSP serial interfaces.
The ADC78H90 may be operated with independent analog
and digital supplies. The analog supply (AVDD) can range
from +2.7V to +5.25V, and the digital supply (DVDD) can
range from +2.7V to AVDD. Normal power consumption using
a +3V or +5V supply is 1.5 mW and 8.3 mW, respectively.
The power-down feature reduces the power consumption to
just 0.3 µW using a +3V supply, or 0.5 µW using a +5V
supply.
The ADC78H90 is packaged in a 16-lead TSSOP package.
Operation over the industrial temperature range of −40˚C to
+85˚C is guaranteed.
Features
n Eight input channels
n Variable power management
n Independent analog and digital supplies
n SPI™/QSPI™/MICROWIRE™/DSP compatible
n Packaged in 16-lead TSSOP
Key Specifications
n Conversion Rate
n DNL
n INL
n Power Consumption
— 3V Supply
— 5V Supply
500 kSPS
± 1 LSB (max)
± 1 LSB (max)
1.5 mW (typ)
8.3 mW (typ)
Applications
n Automotive Navigation
n Portable Systems
n Medical Instruments
n Mobile Communications
n Instrumentation and Control Systems
Connection Diagram
Ordering Information
Order Code
ADC78H90CIMT
ADC78H90CIMTX
ADC78H90EVAL
Temperature Range
−40˚C to +85˚C
−40˚C to +85˚C
20079305
Description
16-Lead TSSOP Package
16-Lead TSSOP Package, Tape & Reel
Evaluation Board
TRI-STATE® is a trademark of National Semiconductor Corporation.
MICROWIRE™ is a trademark of National Semiconductor Corporation.
QSPI™ and SPI™ are trademarks of Motorola, Inc.
© 2004 National Semiconductor Corporation DS200793
www.national.com
1 page  
ADC78H90 Timing Specifications
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500
KSPS, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
Units
Setup Time SCLK High to CS
t1a Falling Edge
(Note 9)
10 ns (min)
Hold time SCLK Low to CS Falling
t1b Edge
(Note 9)
10 ns (min)
t2 Delay from CS Until DOUT active
Data Access Time after SCLK
t3 Falling Edge
30 ns (max)
30 ns (max)
Data Setup Time Prior to SCLK
t4 Rising Edge
10 ns (min)
t5 Data Valid SCLK Hold Time
t6 SCLK High Pulse Width
t7 SCLK Low Pulse Width
CS Rising Edge to DOUT
t8 High-Impedance
10
0.4 x
tSCLK
0.4 x
tSCLK
20
ns (min)
ns (min)
ns (min)
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 10 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. In the 16-pin
TSSOP, θJA is 96˚C/W, so PDMAX = 1,200 mW at 25˚C and 625 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when the ADC78H90 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously,
such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t1a and t1b.
5 www.national.com
5 Page 
Applications Information
1.0 ADC78H90 OPERATION
The ADC78H90 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution
digital-to-analog converter. Simplified schematics of the
ADC78H90 in both track and hold operation are shown in
Figures 1, 2, respectively. In Figure 1, the ADC78H90 is in
track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer,
and SW2 balances the comparator inputs. The ADC78H90 is
in this state for the first three SCLK cycles after CS is
brought low.
Figure 2 shows the ADC78H90 in hold mode: switch SW1
connects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge to or from
the sampling capacitor until the comparator is balanced.
When the comparator is balanced, the digital word supplied
to the DAC is the digital representation of the analog input
voltage. The ADC78H90 is in this state for the last thirteen
SCLK cycles after CS is brought low.
FIGURE 1. ADC78H90 in Track Mode
20079309
FIGURE 2. ADC78H90 in Hold Mode
20079310
The time when CS is low is considered a serial frame. Each
of these frames should contain an integer multiple of 16
SCLK cycles, during which time a conversion is performed
and clocked out at the DOUT pin and data is clocked into the
DIN pin to indicate the multiplexer address for the next
conversion.
2.0 USING THE ADC78H90
A ADC78H90 timing diagram is shown in Figure 3. A serial
interface timing diagram for the ADC78H90 is shown in the
Timing Diagrams section. CS is chip select, which initiates
conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the
timing of serial data. DOUT is the serial data output pin,
where a conversion result is sent as a serial data stream,
MSB first. Data to be written to the ADC78H90’s Control
Register is placed on DIN, the serial data input pin. New data
is written to DIN with each conversion.
11 www.national.com
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| PDF Descargar | [ Datasheet ADC78H90CIMTX.PDF ] | |
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