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ADCMP551 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADCMP551은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ADCMP551 기능
기능 Single Supply High Speed PECL Comparators
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ADCMP551 데이터시트, 핀배열, 회로
Single Supply High Speed PECL Comparators
Preliminary Technical Data
ADCMP551/ADCMP552/ADCMP553
FEATURES
Single power supply
750 ps propagation delay input to output
100 ps propagation delay dispersion
Differential PECL compatible outputs
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 70 dB
750 ps minimum pulse width
Equivalent input rise time bandwidth > 750 MHz
Typical output rise/fall of 500 ps
Programmable Hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP551/
ADCMP552/
ADCMP553
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
Figure 1.
GENERAL DESCRIPTION
The ADCMP551/ADCMP552/ADCMP553 are single supply,
high speed comparators fabricated on Analog Devices’
proprietary XFCB process. The devices feature a 750 ps
propagation delay with less than 150 ps overdrive dispersion.
Dispersion, a measure of the difference in propagation delay
under differing overdrive conditions, is a particularly important
characteristic of high speed comparators. A separate
programmable hysteresis pin is available on the ADCMP552.
A differential input stage permits consistent propagation delay
with a common-mode range from –0.2 V to VCCI – 2.0 V.
Outputs are complementary digital signals are fully compatible
with PECL 10 K and 10 KH logic families. The outputs provide
sufficient drive current to directly drive transmission lines
terminated in 50 Ω to VCCO − 2 V. A latch input is included
and permits tracking, track-and-hold, or sample-and-hold
modes of operation. The latch input pins contain internal pull-
ups that set the latch in tracking mode when left open.
The ADCMP551/ADCMP552/ADCMP553 are specified over
the –40°C to +85°C industrial temperature range. The
ADCMP551 is available in a 16-lead QSOP package; the
ADCMP552 is available in a 20-lead QSOP package; and the
ADCMP553 is available in an 8-lead MSOP package.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




ADCMP551 pdf, 반도체, 판매, 대치품
ADCMP551/ADCMP552/ADCMP553
Parameter
AC PERFORMANCE (continued)
Equivalent Input Rise Time Bandwidth1
Maximum Toggle Rate
Minimum Pulse Width
Unit-to-Unit Propagation Delay Skew
POWER SUPPLY (ADCMP551/ADCMP552)
Input Supply Current
Output Supply Current
Output Supply Current
Input Supply Voltage
Output Supply Voltage
Positive Supply Differential
Power Dissipation
Power Dissipation
DC Power Supply Rejection Ratio—VCCI
DC Power Supply Rejection Ratio—VCCO
POWER SUPPLY (ADCMP553)
Positive Supply Current
Positive Supply Current
Positive Supply Voltage
Power Dissipation
Power Dissipation
DC Power Supply Rejection Ratio — VCC
HYSTERESIS (ADCMP552 Only)
Programmable Hysteresis
Symbol Conditions
BWEQ
PWMIN
0 V to 1 V swing, 2 V/ns
>50% output swing
∆tPD < 50 ps
IVCCI
IVCCO
VCCI
VCCO
VCCO − VCCI
PD
PSRRVCCI
PSRRVCCO
@ 3.3 V
@ 3.3 V without load
@ 3.3 V with load
Dual
Dual
Dual, without load
Dual, with load
IVCC
VCC
PD
PSRRVCC
@ 3.3 V without load
@ 3.3 V with load
Dual
Dual, without load
Dual, with load
Preliminary Technical Data
Min
3.135
3.135
–0.2
3.135
0
Typ Max
750
650
750
100
12.5 16
69
62 70
3.3 5.25
3.3 5.25
+2.3
55 70
115 140
70
70
9 11
35 42
3.3 5.25
30 40
60 75
70
40
Unit
MHz
MHz
ps
ps
mA
mA
mA
V
V
V
mW
mW
dB
dB
mA
mA
V
mW
mW
dB
mV
1 Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BWEQ = .22/(trCOMP2-trIN2), where trIN is the 20/80
input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.
Rev. PrB | Page 4 of 14

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ADCMP551 전자부품, 판매, 대치품
Preliminary Technical Data
ADCMP551/ADCMP552/ADCMP553
ADCMP551
12
13
15
16
Pin No.
ADCMP552
15
16
18
19
ADCMP553
7
Mnemonic
LEB
LEB
QB
QB
VCC
Function
One of Two Complementary Inputs for Channel B Latch Enable. In the compare
mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction
with LEB.
One of Two Complementary Inputs for Channel B Latch Enable. In the compare
mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction
with LEB.
One of Two Complementary Outputs for Channel B. QB is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.
One of Two Complementary Outputs for Channel B. QB is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.
Positive Supply Terminal.
Rev. PrB | Page 7 of 14

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