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PDF ADCMP553 Data sheet ( Hoja de datos )
| Número de pieza | ADCMP553 | |
| Descripción | Single Supply High Speed PECL Comparators | |
| Fabricantes | Analog Devices | |
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Single Supply High Speed PECL Comparators
Preliminary Technical Data
ADCMP551/ADCMP552/ADCMP553
FEATURES
Single power supply
750 ps propagation delay input to output
100 ps propagation delay dispersion
Differential PECL compatible outputs
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 70 dB
750 ps minimum pulse width
Equivalent input rise time bandwidth > 750 MHz
Typical output rise/fall of 500 ps
Programmable Hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP551/
ADCMP552/
ADCMP553
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
Figure 1.
GENERAL DESCRIPTION
The ADCMP551/ADCMP552/ADCMP553 are single supply,
high speed comparators fabricated on Analog Devices’
proprietary XFCB process. The devices feature a 750 ps
propagation delay with less than 150 ps overdrive dispersion.
Dispersion, a measure of the difference in propagation delay
under differing overdrive conditions, is a particularly important
characteristic of high speed comparators. A separate
programmable hysteresis pin is available on the ADCMP552.
A differential input stage permits consistent propagation delay
with a common-mode range from –0.2 V to VCCI – 2.0 V.
Outputs are complementary digital signals are fully compatible
with PECL 10 K and 10 KH logic families. The outputs provide
sufficient drive current to directly drive transmission lines
terminated in 50 Ω to VCCO − 2 V. A latch input is included
and permits tracking, track-and-hold, or sample-and-hold
modes of operation. The latch input pins contain internal pull-
ups that set the latch in tracking mode when left open.
The ADCMP551/ADCMP552/ADCMP553 are specified over
the –40°C to +85°C industrial temperature range. The
ADCMP551 is available in a 16-lead QSOP package; the
ADCMP552 is available in a 20-lead QSOP package; and the
ADCMP553 is available in an 8-lead MSOP package.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltages
Input Supply Voltage (VCCI to GND)
Output Supply Voltage (VCCO to GND)
Ground Voltage Differential
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−0.5 V to +0.5 V
Input Voltages
Input Common-Mode Voltage
−0.5 V to +3.5 V
Differential Input Voltage
−4.0 V to +4.0 V
Input Voltage, Latch Controls
−0.5 V to +5.5 V
Output
Output Current
30 mA
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +85°C
125°C
−65°C to +150°C
ADCMP551/ADCMP552/ADCMP553
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
THERMAL CONSIDERATIONS
The ADCMP551 16-lead QSOP package has a θJA (junction-to-
ambient thermal resistance) of TBD°C/W in still air.
The ADCMP552 20-lead QSOP package has a θJA (junction-to-
ambient thermal resistance) of TBD°C/W in still air.
The ADCMP553 8-lead MSOP package has a θJA (junction-to-
ambient thermal resistance) of TBD°C/W in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 5 of 14
5 Page 
Preliminary Technical Data
APPLICATION INFORMATION
The ADCMP55x series of comparators are very high speed
devices. Consequently, high speed design techniques must be
employed to achieve the best performance. The most critical
aspect of any ADCMP55x design is the use of a low impedance
ground plane. A ground plane, as part of a multilayer board, is
recommended for proper high speed performance. Using a
continuous conductive plane over the surface of the circuit
board can create this, allowing breaks in the plane only for
necessary signal paths. The ground plane provides a low
inductance ground, eliminating any potential differences at
different ground points throughout the circuit board caused by
ground bounce. A proper ground plane also minimizes the
effects of stray capacitance on the circuit board.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close to the power supply
pins as possible on the ADCMP55x to ground. These capacitors
act as a charge reservoir for the device during high frequency
switching.
The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input pins
may be left open. The internal pull-ups on the latch pins set the
latch to transparent mode. If the latch is to be used, valid PECL
voltages are required on the inputs for proper operation. The
PECL voltages should be referenced to VCCI.
Occasionally, one of the two comparator stages within the
ADCMP551/ADCMP552 is not used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
connecting the LATCH ENABLE and LATCH ENABLE inputs
as described previously.
The best performance is achieved with the use of proper PECL
terminations. The open-emitter outputs of the ADCMP55x are
designed to be terminated through 50 Ω resistors to
VCCO − 2.0 V or any other equivalent PECL termination. If high
speed PECL signals must be routed more than a centimeter,
microstrip or stripline techniques may be required to ensure
proper transition times and prevent output ringing.
ADCMP551/ADCMP552/ADCMP553
CLOCK TIMING RECOVERY
Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed
comparator can be used to recover the distorted waveform
while maintaining a minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator amplifier, proper design
and layout techniques should be used to ensure optimal
performance from the ADCMP55x. The performance limits of
high speed circuitry can easily be a result of stray capacitance,
improper ground impedance, or other layout issues.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP55x. Source resistance in combination with equivalent
input capacitance can cause a lagged response at the input, thus
delaying the output. The input capacitance of the ADCMP55x,
in combination with stray capacitance from an input pin to
ground, could result in several picofarads of equivalent
capacitance. A combination of 3 kΩ source resistance and 5 pF
input capacitance yields a time constant of 15 ns, which is
significantly slower than the 750 ps capability of the
ADCMP55x. Source impedances should be significantly less
than 100 Ω for best performance.
Sockets should be avoided due to stray capacitance and induc-
tance. If proper high speed techniques are used, the
ADCMP55x should be free from oscillation when the
comparator input signal passes through the switching threshold.
COMPARATOR PROPAGATION DELAY
DISPERSION
The ADCMP55x has been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
100 mV to 1 V. Propagation delay overdrive dispersion is the
change in propagation delay that results from a change in the
degree of overdrive (how far the switching point is exceeded by
the input). The overall result is a higher degree of timing
accuracy since the ADCMP55x is far less sensitive to input
variations than most comparator designs.
Rev. PrB | Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADCMP553.PDF ] | |
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