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PDF ADCS9888 Data sheet ( Hoja de datos )
| Número de pieza | ADCS9888 | |
| Descripción | 205/170/140 MSPS Video Analog Front End | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 2004
ADCS9888
205/170/140 MSPS Video Analog Front End
General Description
n Output format supports 4:2:2 video pulldown
The ADCS9888 is a high performance Analog Front End
(AFE) for digital video applications at resolutions up to
UXGA. It performs all the analog and mixed signal functions
necessary to digitize a variety of computer and component
video sources. The ADCS9888 has a 3 channel, 8 bit 205
MHz ADC with full DC restoration and gain/offset compen-
sation. Full processing of synchronization signals is included
with on-chip PLL locked to the pixel rate. Digital sync and
analog sync-on-green signals are supported. Flexible data
output modes support a variety of downstream data capture
and processing applications.
Features
n 205 million pixels/s conversion rate
n Digitally programmed gain and offset for red, green and
blue color balancing
n Compatible with RGB and YUV/YPbPr video signals
Key Specifications
n Output data resolution
n Maximum pixel conversion rate
n Analog input bandwidth (typical)
n PLL clock jitter (typical)
n Analog supply voltage
n I/O supply voltage
n Power dissipation (typical)
Applications
n LCD flat panel monitors
n Video projectors
n Plasma display panels
n Video capture hardware
n RGB and YUV video processing
8 bits x 3 channels
205 MHz
500 MHz
570 ps p-p
3.0 V to 3.6 V
2.2 V to 3.6 V
1.3W
Typical Application
Ordering Information
Temperature Range
0˚C ≤ TA ≤ +70˚C
Order Number
Device Marking
ADCS9888CVH1-205
ADCS9888CVH-205
ADCS9888CVH1-170
ADCS9888CVH-170
ADCS9888CVH1-140
Notes:1 - Tray transport media, 66 parts per tray.
ADCS9888CVH-140
20062801
NSC Drawing
VLA128A
© 2004 National Semiconductor Corporation DS200628
www.national.com
1 page  
Pin Descriptions (Continued)
Pin
53
54
29
Serial Interface
31
32
33
Sync. Outputs
125
127
126
Label
COAST
CKEXT
CKINV
Type
Description
Digital Input PLL Clock Generator Coast Input. When enabled via Register 0Fh, Bit 5,
this input will cause the clock generator circuit to run open loop and ignore
the input reference clock. This is useful when operating with sync signals
that contain extra equalization pulses that must be ignored by the PLL. In
many cases, the internal VSOUT signal is used to provide the coast
control signal, but in some cases it is useful to provide an external COAST
control. Please refer to the applications section for more information.
Digital Input External Clock Input (Optional). This input can be used to provide an
external clock source instead of the internally generated clock. It is
enabled via Register 15h, Bit 0. When an external clock is used, most
other internal functions operate normally. When unused, this pin can be
connected to ground directly, or through a 10 kΩ resistor. The sampling
phase adjustment feature is operational when CKEXT is used.
Digital Input Sampling clock Inverting Input. This input can be used to invert the pixel
sampling clock, with respect to the normal phase of operation. This causes
the pixel sampling point to be shifted by 180 degrees in phase. Alternate
pixel sampling mode makes use of this feature by sampling at 1/2 the
incoming pixel rate, and switching the sampling phase by 180 degree
between alternate frames of video. When unused, this input should be
grounded. See the applications section for more information.
SDA
SCL
A0
Digital I/O Serial Control Interface Data Input/Output. The serial interface is used to
access the configuration and status registers in the ADCS9888. Mode and
Data information are transferred through the SDA pin from the host or
master device. Please refer to the applications section of the datasheet
under Serial Communications for more information.
Digital Input Serial Control Interface Clock Input. The clock input is controlled by the
host or master device, and is used to load in the data sent by the host,
and to clock data out of the ADCS9888. Please refer to the applications
section of the datasheet under Serial Communications for more
information.
Digital Input The least significant bit of the device serial address is selectable as 0 or 1
to allow up to 2 ADCS9888 devices to be connected on the same serial
interface. Please refer to the applications section of the datasheet under
Serial Communications for more information.
HSOUT
Digital
Output
VSOUT
Digital
Output
SOGOUT Digital
Output
Horizontal Sync Output. Internally generated and phase aligned horizontal
sync signal. This signal is used as a timing reference for the digital output
data stream. Please refer to the section on sync processing for more
information.
Vertical Sync Output. A delayed version of the input vertical
synchronization signal. Please refer to the section on sync processing for
more information.
Sync-On-Green Output. A logic level signal that is the output of the
Sync-On-Green slicer circuit. Please refer to the section on sync
processing for more information.
5 www.national.com
5 Page 
Analog Channel Characteristics (Continued)
20062804
Note 8: Typical figures are at TJ = TA = 25˚C, with the ADC Clock at the stated speed, and represent most likely parametric norm.
Note 9: Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Full channel integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs from the straight line that best fits the actual
transfer function of the AFE.
Note 11: The output supply current (IDD) includes the power required to drive a typical digital bus and load circuit at the stated test frequency. The actual output
supply current will depend on the load capacitance of the printed circuit board and connected load device, and the operating frequency and output mode in the
application.
Note 12: These values are guaranteed by design and characterization testing.
11 www.national.com
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