PDF ADE3700XT Data sheet ( Hoja de datos )

Número de pieza	ADE3700XT
Descripción	Analog LCD Display Engine for XGA and SXGA Resolutions
Fabricantes	STMicroelectronics
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No Preview Available ! ® ADE3700 Analog LCD Display Engine for XGA and SXGA Resolutions Feature Overview s Programmable Context Sensitive™ Scaling s High-quality Up-scaling and Down-scaling s Integrated 9-bit ADC/PLL s IQSync™ AutoSetup s Integrated programmable Timing Controller s Integrated Pattern Generator s Perfect Picture™ Technology s sRGB 3D Color Warp s Integrated OSD s Advanced EMI reduction features s Framelock operation with Safety Mode™ s Serial I²C interface s Low power 0.18 µm process technology General Description TARGET SPECIFICATION ADE3700 devices are a family of highly-integrated display engine ICs, enabling the most advanced, flexible, and cost-effective system-on-chip solutions for analog-only input LCD display applications. The ADE3700 covers the full range of XGA and SXGA analog-only applications including Smart Panel designs. The ADE3700 family is pin-to-pin compatible and comes in a low-cost, 128-pin LQFP package. ADE3700 devices use the same software platform and are backward-compatible with the previous generation of ADE3xxx Scaling Engines. Analog RGB Video Signals Line-Lock PLL Triple 9-bit ADC Fast and accurate adjustments of: • Phase • Position •Level •Clock ADE 3700 Microcontroller I²C On-Screen Display Engine Interlace Mode Detection IQ Scaling™ Engine with Context Sensitive™ Filtering Firmware ROM Pattern Generator EMI Reduction • Per Pin Delay • Slew Rate Control • Spread Spectrum • Data Inversion sRGB 3D Color Warp Temporal & Spatial Dithering To TFT LCD Panel Programmable Timing Controller (TCON) LCD Scaler Product Selector Product Package Output Format Support Resolution TCON Input Interface Support Analog DVI YUV ADE3700X ADE3700XT ADE3700SX 128 LQFP Up to XGA 75 Hz Yes 128 LQFP Up to XGA 75 Hz Yes Yes 128 LQFP Up to SXGA 75 Hz Yes October 2003 This is preliminary information on a new product forseen to be developed. Details are subject to change without notice. 1/89 1 page ADE3700 1 General Information The ADE3700 family of devices is capable of implementing all of the advanced features of today’s LCD monitor products. For maximum flexibility, an external microcontroller (MCU) is used for controlling the ADE3700 and other monitor functions. Figure 1: ADE3700 Block Diagram DATA CTRL DMEAS Timing Controller Analog Port SMEAS LLKPLL INCLK LCD Scaler SCLK Frequency Synthesizer SCLK Color Management OSD GAMMA LUT Pattern Generator DOTCLK FM Freq. Synthesizer The ADE3700 architecture unburdens the MCU from all data-intensive pixel manipulations, providing an optimal blend of features and code customizing without incurring the cost of a 16-bit processor or memory. The key interactions between the monitor MCU and the ADE3700 can be broken down into the features shown in the table below. Table 1: ADE3700 Features (Sheet 1 of 2) Feature Power-up / Initialize Activity Detect Description of ADE3700 Operation Blocks Used Pages When power is first applied, the ADE3700 is asynchronously reset from a pin. The MCU typically programs the ADE3700 with a number of default values and sets up the ADE3700 to identify activity on any of the input pins. All pre- configured values and RAMs, such as DVI settings, line-lock PLL settings, OSD characters, LCD timing values (output sequencer), scale kernels, gamma curves, sRGB color warp, APC dithering, output pin configuration (OMUX), etc. can be pre-loaded into the ADE3700. The typical end state is that the ADE3700 is initialized into a low power mode, ready to turn active once the power button is pressed. When the monitor has been powered on, the inputs can be monitored for active video sources. Based on the activity monitors, the MCU chooses an input or power down state. GLBL SMEAS LLK ADC OSD SCALER GAMMA SRGB OUTSEQ TCON APC OMUX SMEAS 11 25 18 17 62 42 70 60 45 48 71 72 25 5/89 5 Page ADE3700 2 Functional Description Global Control 2.1 Global Control The global control block is responsible for: q selecting clock sources q power control q I²C control q SCLK frequency synthesizer control q block by block synchronous reset generation The global control block runs on the XCLK clock domain which is required to be active for programming. The clock domains of all other blocks are set in the Global Control Block. For I²C access, the requested block must be driven with a valid clock frequency greater than 10 MHz. Clock domains are shown in Figure 2. Figure 2: Global Control Block Diagram MCU (SCL, SDA) PC Analog INR, G, B V, H, Csync I²C Global PWM Sync Measure XCLK Domain Sync Re-Time ADC (Analog) ADC Digital I/F Data LCD Scaler ADE3700 Flicker Detection Line Lock PLL Data Measure INCLK Domain SCLK Domain SCLK Freq. Synthesizer Output Sequencer TCON DOTCLK Domain FM Freq. Synthesizer ORA OGA OBA ORB OGB OBB OCLK ODE OHS OVS TCON To program the SCLK frequency synthesizer to a desired frequency (fOUT, in MHz), the following equations apply. Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 1 of 2) Frequency Range fOUT < 8 x fXCLK AND fOUT ≥ 4 x fXCLK fOUT < 4 x fXCLK AND fOUT ≥ 2 x fXCLK SDIV 0 1 11/89 11 Page

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