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PDF ADF4001 Data sheet ( Hoja de datos )
| Número de pieza | ADF4001 | |
| Descripción | 200 MHz Clock Generator PLL | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
200 MHz Clock Generator PLL
ADF4001
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REFIN
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an exter-
nal loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
AVDD
DVDD
FUNCTIONAL BLOCK DIAGRAM
VP CPGND
RSET
REFIN
CLK
DATA
LE
RFINA
RFINB
ADF4001
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT
INPUT REGISTER 22
FUNCTION
LATCH
SDOUT
N COUNTER
LATCH
13
13-BIT
N COUNTER
PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
CP
LOCK DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AVDD
SDOUT
MUX
HIGH Z
MUXOUT
REV. B
CE
AGND
DGND
M3 M2 M1
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113
www.analog.com
© 2013 Analog Devices, Inc. All rights reserved.
1 page  
ADF4001
PIN CONFIGURATIONS
RSET 1
CP 2
CPGND 3
AGND 4
RFINB 5
RFINA 6
AVDD 7
REFIN 8
ADF4001
TOP VIEW
(Not to Scale)
16 VP
15 DVDD
14 MUXOUT
13 LE
12 DATA
11 CLK
10 CE
9 DGND
NOTES
1. TRANSISTOR COUNT 6425 (CMOS)
AND 50 (BIPOLAR).
TSSOP
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
ADF4001
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
NOTES
1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR).
2. CONNECT EXPOSED PAD TO AGND.
LFCSP
Table 1. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Description
1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship
between ICP and RSET is
ICP MAX
23.5
RSET
So, with RSET = 4.7 kΩ, ICP MAX = 5 mA.
2 20 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter which,
in turn, drives the external VCO or VCXO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the N counter. This point must be decoupled to the ground
plane with a small bypass capacitor, typically 100 pF. See Figure 3.
6
5
RFINA
Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
7
6, 7 AVDD
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AVDD must have the
same value as DVDD.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits.
14 15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15
16, 17
DVDD
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DVDD must be the
same value as AVDD.
16 18 VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems
where VDD is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
range of up to 5 V.
N/A EP
EPAD
Exposed Pad. The exposed pad should be connected to AGND.
Rev. B | Page 4
5 Page 
ADF4001
Table V. Function Latch Map
RESERVED
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
F4 F3
F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)
X = DON’T CARE
PHASE DETECTOR
F2 POLARITY
0 NEGATIVE
1 POSITIVE
F3 CHARGE PUMP OUTPUT
0 NORMAL
1 THREE-STATE
F4 F5
0X
10
11
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
COUNTER
F1 OPERATION
0 NORMAL
1 R, N COUNTER
HELD IN RESET
CPI6
CPI3
0
0
0
0
1
1
1
1
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CPI5
CPI2
0
0
1
1
0
0
1
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CP14
CPI1
0
1
0
1
0
1
0
1
TIMEOUT
TC2 TC1 (PFD CYCLES)
003
017
1 0 11
1 1 15
0 0 19
0 1 23
1 0 27
1 1 31
0 0 35
0 1 39
1 0 43
1 1 47
0 0 51
0 1 55
1 0 59
1 1 63
2.7k⍀
1.088
2.176
3.264
4.352
5.44
6.528
7.616
8.704
ICP (mA)
4.7k⍀
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
10k⍀
0.294
0.588
0.882
1.176
1.47
1.764
2.058
2.352
CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN
M3 M2 M1 OUTPUT
0 0 0 THREE-STATE OUTPUT
0 0 1 DIGITAL LOCK DETECT
0 1 0 N DIVIDER OUTPUT
0 1 1 AVDD
1 0 0 R DIVIDER OUTPUT
1 0 1 N-CHANNEL OPEN-DRAIN
LOCK DETECT
1 1 0 SERIAL DATA OUTPUT
1 1 1 DGND
–10–
REV. B
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ADF4001.PDF ] | |
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