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PDF ADF4007 Data sheet ( Hoja de datos )
| Número de pieza | ADF4007 | |
| Descripción | High Frequency Divider/PLL Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Frequency Divider/PLL Synthesizer
ADF4007
FEATURES
7.5 GHz bandwidth
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
RSET control of charge pump current
Hardware power-down mode
APPLICATIONS
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
GENERAL DESCRIPTION
The ADF4007 is a high frequency divider/PLL synthesizer that
can be used in a variety of communications applications. It can
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.
It consists of a low noise digital PFD (phase frequency detector), a
precision charge pump, and a divider/prescaler. The divider/
prescaler value can be set by two external control pins to one of
four values (8, 16, 32, or 64). The reference divider is permanently
set to 2, allowing an external REFIN frequency of up to 240 MHz.
A complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and a VCO (voltage
controlled oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high frequency
systems, simplifying system architecture and reducing cost.
FUNCTIONAL BLOCK DIAGRAM
VDD
VP CPGND RSET
REFIN
ADF4007
R COUNTER
÷2
PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
CP
RFINA
RFINB
N COUNTER
÷ 8, ÷ 16,
÷ 32, ÷ 64
MUX
MUXOUT
N2 N1
GND
Figure 1.
M2 M1
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
1 page  
ADF4007
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
CSP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
Infrared (15 s)
Transistor Count
CMOS
Bipolar
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−65°C to +125°C
150°C
122°C/W
215°C
220°C
6425
303
1 GND = AGND = DGND = 0 V.
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. B | Page 4 of 16
5 Page 
ADF4007
MUXOUT
The output multiplexer on the ADF4007 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M2 and M1 pins. Figure 12
shows the MUXOUT section in block diagram form.
DVDD
DVDD
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
MUX
CONTROL
MUXOUT
Data Sheet
PFD Polarity
The PFD polarity is set by the state of M2 and M1 pins as given
in the Table 5. The ability to set the polarity allows the use of VCOs
with either positive or negative tuning characteristics. For standard
VCOs with positive characteristics (output frequency increases
with increasing tuning voltage), the polarity should be set to
positive. This is accomplished by tying M2 and M1 to a logic
low state.
CP Output
The CP output state is also controlled by the state of M2 and M1. It
can be set either to active (so that the loop can be locked) or to
three-state (open the loop). The normal state is CP output active.
Figure 12. MUXOUT Circuit
DGND
Rev. B | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADF4007.PDF ] | |
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