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ADF4106 PDF 데이터시트 ( Data , Function )

부품번호 ADF4106 기능
기능 PLL Frequency Synthesizer
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ADF4106 데이터시트, 핀배열, 회로
Data Sheet
PLL Frequency Synthesizer
ADF4106
FEATURES
GENERAL DESCRIPTION
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
Broadband wireless access
Satellite systems
Instrumentation
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
Wireless LANS
Base stations for wireless radios
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER 22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4106
Figure 1.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2001–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADF4106 pdf, 반도체, 판매, 대치품
Data Sheet
ADF4106
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency6
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
B Version1 B Chips2 (typ) Unit
0.5/6.0
–10/0
300
0.5/6.0
–10/0
300
GHz min/max
dBm min/max
MHz max
Test Conditions/Comments
See Figure 18 for input circuit
For lower frequencies, ensure
slew rate (SR) > 320 V/µs
P=8
325 325
MHz max
P = 16
20/300
0.8/VDD
10
±100
20/300
0.8/VDD
10
±100
MHz min/max
V p-p min/max
pF max
µA max
For f < 20 MHz, ensure SR > 50 V/µs
Biased at AVDD/2 (see Note 55)
104 104
MHz max
ABP = 0, 0 (2.9 ns antibacklash pulse width)
Programmable, see Table 9
5
625
2.5
3.0/11
2
2
5
625
2.5
3.0/11
2
2
mA typ
µA typ
% typ
kΩ typ
nA max
% typ
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Table 9
1 nA typical; TA = 25°C
0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD7 (AIDD + DIDD)
IDD8 (AIDD + DIDD)
IDD9 (AIDD + DIDD)
IP
Power-Down Mode10
(AIDD + DIDD)
1.5
2
1.4
0.6
±1
10
1.4
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
11
11.5
13
0.4
10
1.5
2
1.4
0.6
±1
10
1.4
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
9.0
9.5
10.5
0.4
10
% typ
% typ
V min
V max
µA max
pF max
V min
V min
µA max
V max
V min/V max
V min/V max
mA max
mA max
mA max
mA max
µA typ
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
Open-drain output chosen, 1 kΩ pull-up
resistor to 1.8 V
CMOS output chosen
IOL = 500 µA
AVDD ≤ VP ≤ 5.5V
9.0 mA typ
9.5 mA typ
10.5 mA typ
TA = 25°C
Rev. F | Page 3 of 24

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ADF4106 전자부품, 판매, 대치품
ADF4106
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
(Paddle Soldered)
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Transistor Count
CMOS
Bipolar
Rating
–0.3 V to + 3.6 V
–0.3 V to + 0.3 V
–0.3 V to + 5.8 V
–0.3 V to + 5.8 V
–0.3 V to VDD + 0.3 V
–0.3 V to VP + 0.3 V
–0.3 V to VDD + 0.3 V
±600 mV
–40°C to +85°C
–65°C to +125°C
150°C
112°C/W
30.4°C/W
260°C
40 sec
6425
303
1 GND = AGND = DGND = 0 V.
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. F | Page 6 of 24

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