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ADF4206 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADF4206은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ADF4206 기능
기능 Dual RF PLL Frequency Synthesizers
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ADF4206 데이터시트, 핀배열, 회로
Dual RF PLL Frequency Synthesizers
ADF4206/ADF4208
FEATURES
ADF4206: 550 MHz/550 MHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V power supply
Selectable charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Selectable charge pump currents
On-chip oscillator circuit
Selectable dual modulus prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-wire serial interface
Power-down mode
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base stations for wireless radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
GENERAL DESCRIPTION
The ADF420x family of dual frequency synthesizers are used
to implement local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. Each
synthesizer consists of a low noise, digital, phase frequency detector
(PFD); a precision charge pump; a programmable reference
divider; programmable A and B counters; and a dual modulus
prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in
conjunction with the dual modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REFIN frequencies at the
PFD input. The on-chip oscillator circuitry allows the reference
input to be derived from crystal oscillators.
A complete phase-locked loop (PLL) can be implemented if the
synthesizers are used with an external loop filter and voltage
controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
RF2INA
RF2INB
OSCIN
OSCOUT
CLK
DATA
LE
RF1INA
RF1INB
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
VP1
VP2
N = BP + A
RF2
PRESCALER
OSCILLATOR
22-BIT
DATA
REGISTER
SDOUT
N = BP + A
RF1
PRESCALER
11-BIT RF2
B-COUNTER
6-BIT RF2
A-COUNTER
14-BIT RF2
R-COUNTER
14-BIT RF1
R-COUNTER
11-BIT RF1
B-COUNTER
6-BIT RF1
A-COUNTER
ADF4206/ADF4208
PHASE
COMPARATOR
RF2
LOCK
DETECT
CHARGE
PUMP
CPRF2
OUTPUT
MUX
MUXOUT
RF1
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
CPRF1
DGNDRF1
AGNDRF1 DGNDRF2
Figure 1.
AGNDRF2
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




ADF4206 pdf, 반도체, 판매, 대치품
ADF4206/ADF4208
Parameter
POWER SUPPLIES
VDD1
VDD2
VP
IDD (IDD1 + IDD2)6
ADF4206
ADF4208
IDD1
ADF4206
ADF4208
IDD2
ADF4206
ADF4208
IP (IP1 + IP2)
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(RF1)7
ADF4206
ADF4208
Phase Noise Performance8
ADF4206 (RF1, RF2)
ADF4208 (RF1)
ADF4208 (RF1)
Spurious Signals
RF1, RF2 (20 kHz Loop B/W)
B Version1
2.7/5.5
VDD1
VDD1/6.0
14
21
8
14
7.5
9
1
0.5
−213
−217
−92
−85
−91
−80/−84
B Chips2
2.7/5.5
VDD1
VDD1/6.0
14
21
8
14
7.5
9
1
0.5
−213
−217
−92
−85
−91
−80/−84
Unit
V min/V max
V min/V max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
μA typ
Test Conditions/Comments
VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V
9.5 mA typical at VDD = 3 V, TA = 25°C
14 mA typical at VDD = 3 V, TA = 25°C
5.5 mA typical at VDD = 3 V, TA = 25°C
9 mA typical at VDD = 3 V, TA = 25°C
5 mA typical at VDD = 3 V, TA = 25°C
5.5 mA typical at VDD = 3 V, TA = 25°C
TA = 25°C
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dB typ
@ VCO output
@ 540 MHz output, 200 kHz at PFD
@ 1750 MHz output, 200 kHz at PFD
@ 900 MHz output, 200 kHz at PFD
@ 200 kHz/400 kHz offsets and
200 kHz PFD
1 Operating temperature range for B version: −40°C to +85°C.
2 The B chip specifications are given as typical values.
3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4 AC coupling ensures AVDD/2 bias. VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels.
5 Guaranteed by design. Sample tested to ensure compliance.
6 Typical values apply for VDD = 3 V; P = 32; RF1IN1/RF2IN2 for ADF4206 = 540 MHz; RF1IN1/RF2IN2 for ADF4208 = 900 MHz.
7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
8 The phase noise is measured at 1 kHz, unless otherwise noted. The phase noise is measured with the EVAL-ADF4206EB or the EVAL-ADF4208EB evaluation board and
the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
Rev. A | Page 4 of 24

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ADF4206 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4206/ADF4208
VDD1 1
VP1 2
CPRF1 3
DGNDRF1 4
RF1IN 5
OSCIN 6
OSCOUT 7
MUXOUT 8
ADF4206
TOP VIEW
(Not to Scale)
16 VDD2
15 VP2
14 CPRF2
13 DGNDRF2
12 RF2IN
11 LE
10 DATA
9 CLK
Figure 3. 16-Lead TSSOP Pin Configuration
VDD1 1
VP1 2
CPRF1 3
DGNDRF1 4
RF1IN A 5
RF1IN B 6
AGNDRF1 7
OSCIN 8
OSCOUT 9
MUXOUT 10
ADF4208
TOP VIEW
(Not to Scale)
20 VDD2
19 VP2
18 CPRF2
17 DGNDRF2
16 RF2IN A
15 RF2IN B
14 AGNDRF2
13 LE
12 DATA
11 CLK
Figure 4. 20-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
ADF4206 ADF4208
Pin No. Pin No. Mnemonic
1 1 VDD1
2 2 VP1
3 3 CPRF1
4 4 DGNDRF1
5 5 RF1IN/RF1INA
6 8 OSCIN
7 9 OSCOUT
8 10 MUXOUT
9 11 CLK
10 12 DATA
11 13 LE
12 16 RF2IN/RF2INA
13 17 DGNDRF2
14 18 CPRF2
15 19 VP2
16 20 VDD2
N/A 6
N/A 7
N/A 14
N/A 15
RF1INB
AGNDRF1
AGNDRF2
RF2INB
Description
Positive Power Supply for the RF1 Section. A 0.1 μF capacitor is connected between this pin
and DGNDRF1 (the RF1 ground pin). VDD1 should have a value of between 2.7 V and 5.5 V. VDD1
must have the same potential as VDD2.
Power Supply for the RF1 Charge Pump. This is greater than or equal to VDD.
Output from the RF1 Charge Pump. This is normally connected to a loop filter that drives the
input to an external VCO.
Ground Pin for the RF1 Digital Circuitry.
Input to the RF1 Prescaler. This low level input signal is taken from the RF1 VCO.
Oscillator Input. It has a VDD/2 threshold and is driven from an external CMOS or TTL logic gate.
Oscillator Output.
This multiplexer output allows the IF/RF lock detect, the scaled RF, or the scaled reference
frequency external access. See Figure 30.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded
into one of the four latches, the latch being selected using the control bits.
Input to the RF2 Prescaler. This low level input signal is normally ac-coupled to the external
VCO.
Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives the
input to an external VCO.
Power Supply for the RF2 Charge Pump. This is greater than or equal to VDD.
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 μF capacitor is
connected between this pin and DGNDRF2 (the RF2 ground pin). VDD2 has a value between 2.7 V
and 5.5 V. VDD2 must have the same potential as VDD1.
Complementary Input to the RF1 Prescaler of the ADF4208. This point is decoupled to the
ground plane with a small bypass capacitor.
Ground Pin for the RF1 Analog Circuitry.
Ground Pin for the RF2 Analog Circuitry.
Complementary Input to the RF2 Prescaler. This point is decoupled to the ground plane with a
small bypass capacitor.
Rev. A | Page 7 of 24

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