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PDF ADF4207 Data sheet ( Hoja de datos )
| Número de pieza | ADF4207 | |
| Descripción | Dual RF PLL Frequency Synthesizers | |
| Fabricantes | Analog Devices | |
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Dual RF PLL Frequency Synthesizers
ADF4206/ADF4207/ADF4208
FEATURES
GENERAL DESCRIPTION
ADF4206: 550 MHz/550 MHz
The ADF4206 family of dual frequency synthesizers can be
ADF4207: 1.1 GHz/1.1 GHz
used to implement local oscillators in the upconversion and
ADF4208: 2.0 GHz/1.1 GHz
downconversion sections of wireless receivers and transmitters.
2.7 V to 5.5 V Power Supply
Each synthesizer consists of a low-noise digital PFD (Phase
Selectable Charge Pump Supply (VP) Allows Extended Frequency Detector), a precision charge pump, a programmable
Tuning Voltage in 3 V Systems
reference divider, programmable A and B counters and a dual-
Selectable Charge Pump Currents
modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit)
On-Chip Oscillator Circuit
counters, in conjunction with the dual modulus prescaler (P/P + 1),
Selectable Dual Modulus Prescaler
implement an N divider (N = BP + A). In addition, the 14-bit
RF2: 32/33 or 64/65
reference counter (R Counter), allows selectable REFIN frequen-
RF1: 32/33 or 64/65
cies at the PFD input. The on-chip oscillator circuitry allows
3-Wire Serial Interface
the reference input to be derived from crystal oscillators.
Power-Down Mode
A complete PLL (Phase-Locked Loop) can be implemented if
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
the synthesizers are used with an external loop filter and VCOs
(Voltage Controlled Oscillators).
Base Stations for Wireless Radio (GSM, PCS, DCS,
Control of all the on-chip registers is via a simple 3-wire interface.
CDMA, WCDMA)
The devices operate with a power supply ranging from 2.7 V
Wireless LANS
to 5.5 V and can be powered down when not in use.
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2 VP1 VP2
RF2INA
RF2INB
N = BP + A
RF2
PRESCALER
OSCIN
OSCOUT
CLOCK
DATA
LE
OSCILLATOR
22-BIT
DATA
REGISTER
SDOUT
RF1INA
RF1INB
N = BP + A
RF1
PRESCALER
11-BIT RF2
B-COUNTER
6-BIT RF2
A-COUNTER
14-BIT RF2
R-COUNTER
ADF4206/ADF4207/ADF4208
PHASE
COMPARATOR
RF2
LOCK
DETECT
CHARGE
PUMP
OUTPUT
MUX
CPRF2
MUXOUT
14-BIT RF1
R-COUNTER
11-BIT RF1
B-COUNTER
6-BIT RF1
A-COUNTER
RF1
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
CPRF1
REV. 0
DGNDRF1 AGNDRF1
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DGNDRF2 AGNDRF2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
ADF4206/ADF4207/ADF4208
PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin ADF4206/
No. ADF4207 ADF4208
Function
1 VDD1
2 VP1
3 CPRF1
VDD1
VP1
CPRF1
Positive Power Supply for the RF1 Section. A 0.1 µF capacitor should be connected between
this pin and the RF1 ground pin, DGNDRF1. VDD1 should have a value of between 2.7 V and
5.5 V. VDD1 must have the same potential as VDD2.
Power Supply for the RF1 Charge Pump. This should be greater than or equal to VDD.
Output from the RF1 Charge Pump. This is normally connected to a loop filter which, in
turn, drives the input to an external VCO.
4 DGNDRF1 DGNDRF1 Ground Pin for the RF1 Digital Circuitry.
5 RF1IN
RF1INA
Input to the RF1 Prescaler. This low-level input signal is normally taken from the RF1 VCO.
6 OSCIN
RFINB
Complementary Input to the RF1 Prescaler of the ADF4208. This point should be decoupled to
the ground plane with a small bypass capacitor.
7
OSCOUT
AGNDRF1 Ground Pin for the RF1 Analog Circuitry.
8 MUXOUT OSCIN
Oscillator Input. It has a VDD/2 threshold and can be driven from an external CMOS or TTL
logic gate.
9 CLK
10 DATA
OSCOUT
MUXOUT
Oscillator Output.
This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled
Reference Frequency to be accessed externally. See Table V.
11 LE
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 22-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
12 RF2IN
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
13 DGNDRF2 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected using the control bits.
14 CPRF2
15 VP2
AGNDRF2
RF2INB
Ground Pin for the RF2 Analog Circuitry.
Complementary Input to the RF2 Prescaler. This point should be decoupled to the ground
plane with a small bypass capacitor.
16 VDD2
RF2INA
Input to the RF2 Prescaler. This low-level input signal is normally ac-coupled to the
external VCO.
17 DGNDRF2 Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
18
CPRF2
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives
the input to an external VCO.
19 VP2 Power Supply for the RF2 Charge Pump. This should be greater than or equal to VDD.
20
VDD2
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 µF capacitor
should be connected between this pin and the RF2 ground Pin, DGNDRF2. VDD2 should
have a value between 2.7 V and 5.5 V. VDD2 must have the same potential as VDD1.
TSSOP
PIN CONFIGURATIONS
TSSOP
VDD1 1
16 VDD2
VP1 2 ADF4206/ 15 VP2
CPRF1 3 ADF4207 14 CPRF2
DGNDRF1 4
13 DGNDRF2
RF1IN 5
12 RF2IN
OSCIN
6
TOP VIEW
(Not to Scale)
11
LE
OSCOUT 7
10 DATA
MUXOUT 8
9 CLK
VDD1 1
20 VDD2
VP1 2
19 VP2
CPRF1 3
18 CPRF2
DGNDRF1 4
RF1IN A 5
ADF4208 17 DGNDRF2
16 RF2IN A
RF1IN B 6
15 RF2IN B
AGNDRF1
7
TOP VIEW 14 AGNDRF2
(Not to Scale)
OSCIN 8
13 LE
OSCOUT 9
12 DATA
MUXOUT 10
11 CLK
REV. 0
–5–
5 Page 
ADF4206/ADF4207/ADF4208
Table II. ADF4206 Family Latch Summary
RF2 REFERENCE COUNTER LATCH
14-BIT REFERENCE COUNTER, R
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P4 P3 P2 P5 P1
R14 R13 R12 R11 R10 R9
R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
RF2 AB COUNTER LATCH
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
A6 A5 A4 A3 A2 A1 C2 (0) C1 (0)
RF1 REFERENCE COUNTER LATCH
14-BIT REFERENCE COUNTER, R
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P12 P11 P10 P13 P9
R14 R13 R12 R11 R10 R9
R8 R7 R6 R5 R4 R3 R2 R1 C2 (1) C1 (0)
RF1 AB COUNTER LATCH
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
A6 A5 A4 A3 A2 A1 C2 (1) C1 (1)
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADF4207.PDF ] | |
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