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기능 High Performance ISM Band FSK/ASK Transceiver IC
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ADF7020 데이터시트, 핀배열, 회로
Data Sheet
High Performance, ISM Band,
FSK/ASK Transceiver IC
ADF7020
FEATURES
Low power, low IF transceiver
Frequency bands
431 MHz to 478 MHz
862 MHz to 956 MHz
Data rates supported
0.15 kbps to 200 kbps, FSK
0.15 kbps to 64 kbps, ASK
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 0.3 dBm steps
Receiver sensitivity
−119 dBm at 1 kbps, FSK
−112 dBm at 9.6 kbps, FSK
−106.5 dBm at 9.6 kbps, ASK
Low power consumption
19 mA in receive mode
26.8 mA in transmit mode (10 dBm output)
−3 dBm IIP3 in high linearity mode
On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC) compensates
for ±25 ppm crystal at 862 MHz to 956 MHz or±50 ppm at
431 MHz to 478 MHz
Digital RSSI
Integrated Tx/Rx switch
Leakage current of <1 μA in power-down mode
APPLICATIONS
Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice
RSET
CREG[1:4]
FUNCTIONAL BLOCK DIAGRAM
ADCIN
MUXOUT
RLNA
LDO(1:4)
OFFSET
CORRECTION
TEMP
SENSOR
TEST MUX
ADF7020
RFIN
RFINB
RFOUT
LNA
GAIN
IF FILTER
RSSI
MUX 7-BIT ADC
FSK/ASK
DEMODULATOR
OFFSET
CORRECTION
AGC
CONTROL
FSK MOD
CONTROL
GAUSSIAN
FILTER
Σ-
MODULATOR
AFC
CONTROL
DIVIDERS/
MUXING
DIV P
N/N + 1
VCO
CP PFD
DIV R
OSC
CLK
DIV
DATA
SYNCHRONIZER
Tx/Rx
CONTROL
SERIAL
PORT
VCOIN CPOUT
OSC1 OSC2
Figure 1.
CLKOUT
CE
DATA CLK
DATA I/O
INT/LOCK
SLE
SDATA
SREAD
SCLK
Rev. E
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Technical Support
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ADF7020 pdf, 반도체, 판매, 대치품
ADF7020
GENERAL DESCRIPTION
The ADF7020 is a low power, highly integrated FSK/ASK/OOK
transceiver designed for operation in the license-free ISM bands
at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed
Japanese RFID band at 950 MHz. A Gaussian data filter option
is available to allow either GFSK or G-ASK modulation, which
provides a more spectrally efficient modulation. In addition to
these modulation options, the ADF7020 can also be used to
perform both MSK and GMSK modulation, where MSK is a
special case of FSK with a modulation index of 0.5. The modula-
tion index is calculated as twice the deviation divided by the
data rate. MSK is spectrally equivalent to O-QPSK modulation
with half-sinusoidal Tx baseband shaping, so the ADF7020 can
also support this modulation option by setting up the device in
MSK mode.
This device is suitable for circuit applications that meet the
European ETSI-300-220, the North American FCC (Part 15),
or the Chinese Short Range Device regulatory standards. A
complete transceiver can be built using a small number of
external discrete components, making the ADF7020 very
suitable for price-sensitive and area-sensitive applications.
The transmitter block on the ADF7020 contains a VCO and
low noise fractional-N PLL with an output resolution of
<1 ppm. This frequency agile PLL allows the ADF7020 to be
used in frequency-hopping spread spectrum (FHSS) systems.
The VCO operates at twice the fundamental frequency to
reduce spurious emissions and frequency-pulling problems.
Data Sheet
The transmitter output power is programmable in 0.3 dB steps
from −16 dBm to +13 dBm. The transceiver RF frequency and
modulation are programmable using a simple 3-wire interface.
The device operates with a power supply range of 2.3 V to 3.6 V
and can be powered down when not in use.
A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable
features, including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application.
The receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.
An on-chip ADC provides readback of an integrated temperature
sensor, an external analog input, the battery voltage, or the RSSI
signal, which provides savings on an ADC in some applications.
The temperature sensor is accurate to ±10°C over the full operating
temperature range of −40°C to +85°C. This accuracy can be
improved by doing a 1-point calibration at room temperature
and storing the result in memory.
Rev. E | Page 4 of 47

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ADF7020 전자부품, 판매, 대치품
Data Sheet
ADF7020
Parameter
REFERENCE INPUT
Crystal Reference
External Oscillator
Load Capacitance
Crystal Start-Up Time
Input Level
ADC PARAMETERS
INL
DNL
TIMING INFORMATION
Chip Enabled to Regulator Ready
Chip Enabled to RSSI Ready
Tx to Rx Turnaround Time
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
Control Clock Input
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
CLKOUT Rise/Fall
CLKOUT Load
TEMPERATURE RANGE, TA
POWER SUPPLIES
Voltage Supply
VDD
Transmit Current Consumption
−20 dBm
−10 dBm
0 dBm
10 dBm
10 dBm
Receive Current Consumption
Low Current Mode
High Sensitivity Mode
Power-Down Mode
Low Power Sleep Mode
Min
3.625
3.625
Typ
33
2.1
1.0
0.7 ×
VDD
±1
±1
10
3.0
150 µs +
(5 × TBIT)
DVDD −
0.4
−40
Max Unit
Test Conditions
24 MHz
24 MHz
pF See crystal manufacturer’s specification sheet
ms 11.0592 MHz crystal, using 33 pF load capacitors
ms Using 16 pF load capacitors
CMOS levels See the Reference Input section
LSB From 2.3 V to 3.6 V, TA = 25°C
LSB From 2.3 V to 3.6 V, TA = 25°C
µs CREG = 100 nF
ms See Table 11 for more details
Time to synchronized data out, includes AGC settling;
see the AGC Information and Timing section
V
0.2 ×
VDD
±1
10
50
V
µA
pF
MHz
V
0.4 V
5 ns
10 pF
+85 °C
IOH = 500 µA
IOL = 500 µA
2.3
14.8
15.9
19.1
28.5
26.8
19
21
0.1
3.6 V
mA
mA
mA
mA
mA
mA
mA
1 µA
All VDD pins must be tied together
FRF = 915 MHz, VDD = 3.0 V,
PA is matched to 50 Ω
Combined PA and LNA matching network as on
EVAL-ADF7020DBZ1 through EVAL-ADF7020DBZ3
boards, VCO_BIAS_SETTING = 12
PA matched separately with external antenna
switch, VCO_BIAS_SETTING = 12
1 Higher data rates are achievable, depending on local regulations.
2 For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.
3 For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.
4 Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5 For matching details, see the LNA/PA Matching section and the AN-764 Application Note.
6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
7 See Table 5 for a description of different receiver modes.
8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Rev. E | Page 7 of 47

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