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PDF HSP50210 Data sheet ( Hoja de datos )
| Número de pieza | HSP50210 | |
| Descripción | Digital Costas Loop | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HSP50210
January 1999 File Number 3652.4
Digital Costas Loop
The Digital Costas Loop (DCL) performs many of the
baseband processing tasks required for the demodulation of
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
waveforms. These tasks include matched filtering, carrier
tracking, symbol synchronization, AGC, and soft decision
slicing. The DCL is designed for use with the HSP50110
Digital Quadrature Tuner to provide a two chip solution for
digital down conversion and demodulation.
The DCL processes the In-phase (I) and quadrature (Q)
components of a baseband signal which have been digitized
to 10 bits. As shown in the block diagram, the main signal
path consists of a complex multiplier, selectable matched
filters, gain multipliers, cartesian-to-polar converter, and soft
decision slicer. The complex multiplier mixes the I and Q
inputs with the output of a quadrature NCO. Following the
mix function, selectable matched filters are provided which
perform integrate and dump or root raised cosine filtering
(α ~ 0.40). The matched filter output is routed to the slicer,
which generates 3-bit soft decisions, and to the cartesian-to-
polar converter, which generates the magnitude and phase
terms required by the AGC and Carrier Tracking Loops.
The PLL system solution is completed by the HSP50210
error detectors and second order Loop Filters that provide
carrier tracking and symbol synchronization signals. In
applications where the DCL is used with the HSP50110,
these control loops are closed through a serial interface
between the two parts. To maintain the demodulator
performance with varying signal power and SNR, an internal
AGC loop is provided to establish an optimal signal level at
the input to the slicer and to the cartesian-to-polar converter.
Features
• Clock Rates Up to 52MHz
• Selectable Matched Filtering with Root Raised Cosine or
Integrate and Dump Filter
• Second Order Carrier and Symbol Tracking Loop
Filters
• Automatic Gain Control (AGC)
• Discriminator for FM/FSK Detection and Discriminator
Aided Acquisition
• Swept Acquisition with Programmable Limits
• Lock Detector
• Data Quality and Signal Level Measurements
• Cartesian to Polar Converter
• 8-Bit Microprocessor Control - Status Interface
• Designed to work with the HSP50110 Digital
Quadrature Tuner
• 84 Lead PLCC
Applications
• Satellite Receivers and Modems
• BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
Demodulators
• Digital Carrier Tracking
• Related Products: HSP50110 Digital Quadrature Tuner,
D/A Converters HI5721, HI5731, HI5741
• HSP50110/210EVAL Digital Demod Evaluation Board
Block Diagram
CARRIER
TRACK
CONTROL
HI/LO
I SER OR
IIN (9-0)
SERCLK
OR CLK
Q SER OR
QIN (9-0)
SYMBOL
TRACK
CONTROL
CONTROL/
STATUS
BUS
(COF)
LEVEL
DETECT
NCO
COS SIN
10
CARRIER ACQ/TRK
LOOP FILTER
I RRC
FILTER
10 Q RRC
FILTER
(SOF)
13
SYMBOL
TRACKING
LOOP FILTER
CONTROL
INTERFACE
LOOP
FILTER
INTEGRATE/
DUMP
INTEGRATE/
DUMP
SYMBOL
PHASE
ERROR
DETECT
CARRIER PHASE
ERROR DETECT
LEVEL
DETECT
8
CARTESIAN
TO
8 POLAR
LOCK
DETECT
8 MAGNITUDE
8 PHASE
3
SLICER
3
Q
I
LKINT
THRESH
A
OUT(9-0)
10
10
B
OUT(9-0)
SMBLCLK
OEA
OEB
3-253
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HSP50210
Functional Description
The HSP50210 Digital Costas Loop (DCL) contains most of
the baseband processing functions needed to implement a
digital Costas Loop Demodulator. These functions include
LO generation/mixing, matched filtering, AGC, carrier phase
and frequency error detection, timing error detection, carrier
loop filtering, bit sync loop filtering, lock detection,
acquisition/tracking control, and soft decision slicing for
forward error correction algorithms. While the DCL is
designed to work with the HSP50110 Digital Quadrature
Tuner (DQT) as a variable rate PSK demodulator for satellite
demodulation, functions on the chip are common to many
communications receivers.
The DCL provides the processing blocks for the three
tracking loops commonly found in a data demodulator: the
Automatic Gain Control (AGC) loop, the Carrier Tracking
Loop, and a Symbol Tracking Loop. The AGC loop adjusts
for input signal power variations caused by path loss or
signal-to-noise variations. The carrier tracking loop removes
the frequency and phase uncertainties in the carrier due to
oscillator inaccuracies and doppler. The symbol tracking
loop removes the frequency and phase uncertainties in the
data and generates a recovered clock synchronous with the
received data. Each loop consists of an error detector, a loop
filter, and a frequency or gain adjustment/control. The AGC
loop is internal to the DCL, while the symbol and carrier
tracking loops are closed external to the DCL. When the
DCL is used together with the HSP50110, the tracking loops
are closed around the baseband filtering to center the signal
in the filter bandwidth. In addition, the AGC function is
divided between the two chips with the HSP50110 providing
the coarse AGC, and the HSP50210 providing the fine or
final AGC.
A top level block diagram of the HSP50210 is shown in
Figure 1. This diagram shows the major blocks and the
multiplexers used to reconfigure the data path for various
architectures.
Input Controller
In-Phase (I) and Quadrature (Q) data enters the part through
the Input Controller. The 10-bit data enters in either serial or
parallel fashion using either two’s complement or offset
binary format. The input mode and binary format is set in the
Data Path Configuration Control Register, bits 14 and 15
(see Table 14).
If Parallel Input mode is selected, I and Q data are clocked
into the part through IIN0-9 and QIN0-9 respectively. Data
enters the processing pipeline when the input enable
(SYNC) is sampled “low” by the processing clock (CLK). The
enable signal is pipelined with the data to the various
processing elements to minimize pipeline delay where
possible. As a result, the pipeline delay through the AGC,
Carrier Tracking, and Symbol Tracking Loop Filters is
measured in CLKs; not input data samples.
If serial input mode is selected, the I and Q data enters via
the ISER and QSER pins using SERCLK and SSYNC. The
beginning of a serial word is designated by asserting
SSYNC ‘high’ one SERCLK prior to the first data bit, as
shown in Figure 2. On the following SERCLK’s, data is
shifted into the register until all 10 bits have been input. Data
shifting is then disabled and the contents of the register are
held until the next assertion of SSYNC. The assertion of a
SSYNC transfers data into the processing pipeline, and the
Shift Register is enabled to accept new data on the following
SERCLK. When data is transferred to the processing
pipeline by SSYNC, a processing enable is generated which
follows the data through the pipeline. This enable allows the
delay through processing elements (like the loop filters) to be
minimized since their pipeline delay is expressed in CLKs
not SSYNC periods. Note: SSYNC should not be
asserted for more than one SERCLK cycle.
SERCLK
SSYNC
ISER/
QSER
MSB
MSB
SSYNC LEADS 1st DATA BIT
NOTE: Data must be loaded MSB first.
FIGURE 2. SERIAL INPUT TIMING FOR ISER AND QSER INPUTS
Input Level Detector
The Input Level Detector generates a one-bit error signal for
an external IF AGC filter and amplifier. The error signal is
generated by comparing the magnitude of the input samples
to a user programmable threshold. The HI/LO pin is then
driven “high” or “low” depending on the relationship of its
magnitude to the threshold. The sense of the HI/LO pin is
programmable so that a magnitude exceeding the threshold
can either be represented as a “high” or “low” logic state.
The Input Level Detector (HI/LO output) threshold and the
sense are set by the Data Path Configuration Control
Register bits 16-23 and 13 (see Table 14). Note: The Input
Level Detector is typically not used in applications
which use the HSP50210 with the HSP50110.
The high/low outputs can be integrated by an external loop
filter to close an AGC loop. Using this method, the gain of
the loop forces the median magnitude of the input samples
to the threshold. When the magnitude of half of the samples
is above the threshold (and half is below), the error signal is
integrated to zero by the loop filter.
The magnitude of the complex input is estimated by:
Mag (I, Q) = I + 0.375 × Q if I > Q and
Mag (I, Q) = Q + 0.375 × I if Q > I
(EQ. 1)
3-257
5 Page 
HSP50210
AGC LOOP FILTER
AGC AGC
UPPER LOWER
LIMIT † LIMIT †
AGC LOOP
GAIN
MANTISSA †
(2-7 TO 2-14)
AGC LOOP
GAIN
EXPONENT †
(0.000 TO 0.9375)
AGC ERROR DETECT
COMPARE
R
E
G
READ
REG
AGC GAIN = (1.0 + M) x 2E
R
L
I
EM
GI
T
S
RHR
+
E
G
I
F
T
E
G
M
U
X
“0”
0.000 TO 1.07297(2-7)
ENABLE AGC †
POWER
THRSHLD †
GAIN
ERROR
+
-
AGC THRSHLD †
GAIN
ADJUST
GAGC
I
Q
1.0000 TO 15.8572 = GAGC
(0 TO 24dB) CART/POLAR INPUT SELECT†
M
L
I&D FILTER
U
IX
M
I
T I&D FILTER
CARTESIAN TO POLAR
G = 1----.-26----4--
1.0 I2+Q2 0.8
TAN-1(QI )
THRESH
dcloutlvl = agc thresh1----.-2-6---4--
where dcloutlvl is the
magnitude output expressed
in dB from Full Scale (dBFS)
MAGNITUDE
(0 - 1.1455)
PHASE
† Indicates a microprocessor control signal.
FIGURE 7. AGC LOOP BLOCK DIAGRAM
The AGC Loop Filter integrates the scaled error signal to
provide a correction control term to the multipliers in the I and
Q path. The loop filter accumulator has internal upper and
lower limiters. The upper eight bits of the accumulator output
map to an exponent and mantissa format that is used to set
these upper and lower limits. The format, illustrated in Figure
8, is used for the AGC Upper Limit, AGC Lower Limit and the
Correction Control Term (AGC output). This format should not
be confused with the similar format used for the AGC Loop
Gain. The input to the AGC Loop Filter is included in Figure 8
to show the relative weighting of the input to output of the loop
filter. The loop filter input is represented as the eleven letter
“G”s. Lower case “e” and “m” detail the format for the AGC
Upper and Lower Limits. This change in type case should help
keep the AGC Limits and AGC Gain formats from being
confused. The AGC Upper and Lower Limits are set in the
AGC Loop Parameters Control Register, bits 0-15, (see Table
16). This 6-bit unsigned mantissa format provides for an AGC
output control range from 0.0000 to 0.9844, with a resolution
of 0.015625. The 2-bit exponent format provides an AGC
output control range from 1 to 8. The decimal values for each
of the 64 binary mantissa values is detailed in Table 4, while
Table 5 details the decimal value for the 4 exponent values.
The AGC Output is implemented in the multiplier according
to Equation 8.
OutAGC – linear = (1.0 + mAGC)(2e)
(EQ. 8A)
OutAGC – dB = 20 log [(1.0 + mAGC)(2e)]
(EQ. 8B)
where m and e are the binary values for mantissa and
exponent found in Tables 4 and 5.
NOTE:This format is identical to the format used to program the
AGC Upper and Lower Limits, but in this usage it is not a pro-
grammed value. It is a representation of the digital AGC output
number which is presented to the Gain Adjuster (multipliers) to
correct the gain of the I and Q data signals in the main data path.
These equations yield a composite (mantissa and
exponent) AGC output range of 0.0000 to 1.9844(23) which
is a logarithmic range from 0 to 24dB. Figure 9 has graphed
the results of Equation 8 for both the linear and logarithmic
equations. Figure 9 also has a linear estimate of the
logarithmic equation. This linear approximation will be used
in calculating the AGC response time.
21 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18
e e .m m m m m m G G G G G G G G G G G
FIGURE 8. AGC OUTPUT AND AGC LIMITS BIT WEIGHTING
3-263
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HSP50210.PDF ] | |
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