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부품번호 HSP50214AVI 기능
기능 Programmable Downconverter
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HSP50214AVI 데이터시트, 핀배열, 회로
HSP50214A
[ /Title
(HSP5
0214A
)
/Sub-
ject (
Pro-
gram-
mable
Down-
con-
verter)
/Autho
r ()
/Key-
words
(Inter-
sil
Semi-
con-
ductor,
Down-
con-
verter,
Down
Con-
verter,
Pro-
gram-
mable
Down-
con-
verter,
DSP,
AMPS,
TDMA
, North
Ameri-
can
December 1999
Features
POSSOIBBLSEOSLHUESBTPSE5T0PIT2RU1O4TDBEUPCRTODUCT
Programmable Downconverter
Description
• Up to 65 MSPS Front-End Processing Rates (CLKIN) and
55 MSPS (41 MSPS Using the Discriminator) Back-End
Processing Rates (PROCCLK)
Clocks May Be Asynchronous
• Processing Capable of >100dB SFDR
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to 12.94 MSPS with Output Band-
widths to 982kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and Car-
rier Tracking
• Digital Resampling Filter for Symbol Tracking Loops and
Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Slew Rate to
Optimize Output Signal Resolution; Fixed or Auto Gain
Adjust
• Serial, Parallel, and FIFO 16-Bit Output Modes
• Cartesian to Polar Converter and Frequency Discriminator
for AFC Loops and Demodulation of AM, FM, FSK, and
DPSK
• Input Level Detector for External I.F. AGC Support
Applications
• Single Channel Digital Software Radio Receivers
• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA
• Compatible with HSP50210 Digital Costas Loop for PSK
Reception
• Evaluation Platform Available
The HSP50214A Programmable Downconverter converts dig-
itized IF data into filtered baseband data which can be pro-
cessed by a standard DSP microprocessor. The
Programmable Downconverter (PDC) performs down conver-
sion, decimation, narrowband low pass filtering, gain scaling,
resampling, and Cartesian to Polar coordinate conversion.
The 14-bit sampled IF input is down converted to baseband
by digital mixers and a quadrature NCO, as shown in the
Block Diagram. A decimating (4 to 32) fifth order Cascaded
Integrator-Comb (CIC) filter can be applied to the data
before it is processed by up to 5 decimate-by-2 halfband fil-
ters. The halfband filters are followed by a 255-tap pro-
grammable FIR filter. The output data from the
programmable FIR filter is scaled by a digital AGC before
being re-sampled in a polyphase FIR filter. The output sec-
tion can provide seven types of data: Cartesian (I, Q), polar
(R, q), filtered frequency (dq/dt), Timing Error (TE), and
AGC level in either parallel or serial format.
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
HSP50214AVC 0 to 70 120 Ld MQFP
HSP50214AVI -40 to 85 120 Ld MQFP
PKG. NO.
Q120.28x28
Q120.28x28
Block Diagram
C(7:0)
IN(13:0)
GAIN
ADJ
(2:0)
COF
SOF
CLKIN
PROCCLK
REFCLK
MICROPROCESSOR
READ/WRITE
CONTROL
LEVEL DETECT
5TH
ORDER
CIC
FILTER
CARRIER
NCO
5TH
ORDER
CIC
FILTER
RESAMPLING
NCO
AGC LOOP FILTER
AGC
POLYPHASE
FIR AND
HALFBAND
FILTERS
POLYPHASE
FIR AND
HALFBAND
FILTERS
I OUT
CARTESIAN
TO
POLAR
COORDINATE
CONVERTER
MAG.
PHASE
Q OUT
FREQ
DISCRIMINATOR
TIMING ERROR
SEROUTA
SEROUTB
AOUT(15:0)
BOUT(15:0)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
File Number 4449.1




HSP50214AVI pdf, 반도체, 판매, 대치품
HSP50214A
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
DATARDY
OEAH
O Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is
available. DATARDY is asserted for one PROCCLK cycle during the first clock cycle that data is avail-
able on the parallel out busses. See Output Section.
I Output enable for the MSByte of the AOUT bus. Active Low.
OEAL
OEBH
I Output enable for the LSByte of the AOUT bus. Active Low.
I Output enable for the MSByte of the BOUT bus. Active Low.
OEBL
SEL(2:0)
I Output enable for the LSByte of the BOUT bus. Active Low.
I Select Address is used to choose which information in a data set from the Buffer RAM Output Port is
sent to the least significant bytes of AOUT and BOUT. SEL2 is the MSB.
INTRRP
SEROUTA
O Interrupt Output. Active Low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM
Output Port is ready for reading.
O Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGC information can
be sequenced in programmable order. See Output Section and Microprocessor Write Section.
SEROUTB
SERCLK
O Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency,
timing error and AGC information can be sequenced in programmable order. See Output Section and
Microprocessor Write Section.
O Output Clock for Serial Data Out. Derived from PROCCLK as given by Control Word 20 in the Micro-
processor Write Section.
SERSYNC
SEROE
O Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor
Write Section.
I Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are
set to a high impedance.
C(7:0)
A(2:0)
I/O Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB.
I Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB.
WR I Processor Interface Write Strobe. C(7:0) is written to Control Words selected by A(2:0) in the Pro-
grammable Down Converter on the rising edge of this signal. See Microprocessor Write Section.
RD I Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0)
in the Programmable Down Converter on the falling edge of this signal. See Microprocessor Read
Section.
REFCLK
MSYNCO
I Reference Clock. Used as an input clock for the timing error detector. The timing error is computed
relative to REFCLK. REFCLK frequency must be less than or equal to PROCCLK/2.
O Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are
asynchronous. MSYNCO is the synchronization signal between the input section operating under
CLKIN and the back end processing operating under PROCCLK. This output sync signal from one
part is connected to the MSYNCI signal of all the HSP50214As.
MSYNCI
I Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part.
SYNCIN1
NOTE: MSYNCI must be connected to an MSYNCO signal for operation.
I CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC Section, carrier NCO
update, or both. See the Multiple Chip Synchronization Section and Control Word 0 in the Micropro-
cessor Write Section. Active High.
SYNCIN2
SYNCOUT
I FIR/Timing NCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO
update, AGC gain update, or any combination of the above. See the Multiple Chip Synchronization
Section and Control Words 7, 8, and 10 in the Microprocessor Write Section. Active High.
O Strobe Output. This synchronization signal is generated by the µP interface for synchronizing multiple
parts. Can be generated by PROCLK or CLKIN (see Control Word 0 and Control Word 24 in the Mi-
croprocessor Write Section). Active High.
4

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HSP50214AVI 전자부품, 판매, 대치품
HSP50214A
TABLE 2. CELLULAR BASESTATION APPLICATIONS USING
TDMA
STANDARD
GSM
PCN
IS-54
TYPE Cellular
Cellular
Cellular
BASESTATION RX 935-960 1805-1880 824-849
BAND (MHz)
CHANNEL BW (kHz) 200
200
30
# TRAFFIC CHANNELS
8
16
3
VOICE MODULATION GMSK
GMSK
π/4
DQPSK
CHANNEL RATE (Kbps) 270.8
270.8
48.6
CONTROL GMSK
MODULATION
GMSK
π/4
DQPSK
CHANNEL RATE (Kbps) 270.8
270.8
48.6
Several applications are combinations of frequency and time
domain multiple access schemes. For example, GSM is a
TDMA signal that is frequency hopped. The individual chan-
nels contain Gaussian MSK modulated signals. The PDC
again offers the 0.012Hz tuning resolution for de-hopping the
received signal. The combination of halfband and 256-tap
programmable, 22-bit coefficient FIR filters readily performs
the necessary matched filtering for demodulation and opti-
mum detection of the GMSK signals.
CDMA Based Standards and Applications
For Code Division Multiple Access (CDMA) type signals, the
PDC offers the ability to have a single wideband RF front
end, from which it can select a single spread channel of
interest. The synchronization circuitry provides for easy con-
trol of multiple PDC for applications where multiple received
signals are required, such as base-stations.
In IS-95 CDMA, the receive signal bandwidth is approxi-
mately 1.2288MHz wide with many spread spectrum chan-
nel in the band. The PDC supplies the downconversion and
filtering required to receive a single RF channel in the pres-
ence of strong adjacent interference. Multiple PDC’s would
be sourced from a single receive RF chain, each processing
a different receive frequency channel. The despreader would
usually follow the PDC. In some very specific applications,
with short, fixed codes, the filtering and despreading may be
possible with innovative use of the programmable, 22-bit
coefficient FIR filter. The PDC offers 0.012Hz resolution on
tuning to the desired receive channel and excellent rejection
of the portions of the band not being processed, via the half-
band and 255-tap programmable, 22-bit coefficient FIR filter.
Traditional Modulation Formats
AM, ASK, FM and FSK
The PDC has the capability to fully demodulate AM and FM
modulated waveforms. The PDC outputs 15 bits of amplitude or
16 bits of frequency for these modulation formats. The FM dis-
criminator has a 63-tap programmable, 22-bit coefficient FIR fil-
ter for additional signal conditioning of the FM signal. Digital
versions of these formats, ASK and FSK are also readily pro-
cessed using the PDC. Just as in the AM modulated case, ASK
signals will use 15-bit magnitude output of the Cartesian to
Polar Coordinate converter. Multi-tone FSK can be processed
several ways. The frequency information out of the discrimina-
tor can be used to identify the received tone, or the filter can be
used to identify and power detect a specific tone of the received
signal. AMPS is an example of an FM application.
PM and PSK
The PDC provides the downconversion, demodulation,
matched filtering and coordinate conversion required for
demodulation of PM and PSK modulated waveforms. These
modulation formats will require external carrier and symbol
timing recovery loop filters to complete the receiver design.
The PDC was designed to interface with the HSP50210 Dig-
ital Costas Loop to implement the carrier phase and symbol
timing recovery loop filters (for continuous PSK signals - not
burst).
Digital modulation formats that combine amplitude and
phase for symbol mapping, such as m-ary QAM, can also be
downconverted, demodulated, and matched filtered. The
received symbol information is provided with 16 bits of reso-
lution in either Cartesian or Polar coordinates to facilitate
remapping into bits and to recover the carrier phase. Exter-
nal Symbol mapping and Carrier Recovery Loop Filtering is
required for this waveform.
Resampling and Interpolation Filters
Two key features of the resampling FIR filter are that the res-
ampler filter allows the output sample rate to be programmed
with millihertz resolution and that the output sample rate can
be phase locked to an independent separate clock. The res-
ampler frees the front end sampling clocks from having to be
synchronous or integrally related in rate to the baseband
output. The asynchronous relationship between front end
and back end clocks is critical in applications where ISDN
interfaces drive the baseband interfaces, but the channel
sample rates are not related in any way. The interpolation
halfband filters can increase the rate of the output when nar-
row frequency bands are being processed. The increase in
output rate allows maximum use of the programmable FIR
while preserving time resolution in the baseband data.
14-Bit Input and Processing Resolution
The PDC maintains a minimum of 14 bits of processing reso-
lution through to the output, providing over 84dB of dynamic
range. The 18 bits of resolution on the internal references
provide a spurious floor that is better than 98dBc. Further-
more, the PDC provides up to 42dB of gain scaling to com-
pensate for any change in gain in the RF front end as well as
up to 96dB of gain in the internal PDC AGC. This gain maxi-
mizes the output resolution for small signals and compen-
sates for changes in the RF front end gain, to handle
changes in the incoming signal.
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부품번호상세설명 및 기능제조사
HSP50214AVC

Programmable Downconverter

Intersil Corporation
Intersil Corporation
HSP50214AVI

Programmable Downconverter

Intersil Corporation
Intersil Corporation

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