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기능 Digital UpConverter
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HSP50215VC 데이터시트, 핀배열, 회로
Data Sheet
HSP50215
January 1999 File Number 4346.4
Digital UpConverter
The HSP50215 Digital UpConverter (DUC) is a QASK/FM
modulator/FDM upconverter designed for high dynamic range
applications such as cellular basestations. The DUC combines
shaping and interpolation filters, a complex modulator, and
Timing and Carrier NCO’s into a single package. Each DUC
can create a single FDM channel. Multiple DUC’s can be
cascaded digitally for multi-channel applications.
The HSP50215 supports both vector and FM modulation. In
vector modulation mode, the DUC accepts 16-bit I and Q
samples to generate virtually any quadrature AM or PM
modulation format. The DUC also has two FM modulation
modes. In the FM with pulse shaping mode, the 16-bit
frequency samples are pulse shaped/bandlimited prior to FM
modulation. No bandlimiting filter follows the FM modulator.
This FM mode is useful for GMSK type modulation formats. In
the FM with bandlimiting filter mode, the 16-bit frequency
samples directly drive the FM modulator. The FM modulator
output is filtered to limit the spectral occupancy. This FM mode
is useful for analog FM or FSK modulation formats.
The DUC includes an NCO driven interpolation filter, which
allows the input and output sample rate to have a non-
integer or variable relationship. This re-sampling feature
simplifies cascading modulators with sample rates that do
not have harmonic or integer frequency relationships.
The DUC offers digital output spectral purity that exceeds
85dB at the maximum output sample rate of 52 MSPS, for
input sample rates as high as 300 KSPS.
A 16-bit microprocessor compatible interface is used to load
configuration and baseband data. A programmable FIFO depth
interrupt simplifies the interface to the I and Q input FIFOs.
Block Diagram
CAS(15:0)
CASZ
IIN(15:0)
QIN(15:0)
IFIFO
QFIFO
Features
• Output Sample Rates Up to 52 MSPS (48 MSPS
Industrial); Input Data Rates Up to 3.25 MSPS
• I/Q Vector, FM, and Shaped FM Modulation Formats
• 32-Bit Programmable Carrier NCO; 30-Bit Programmable
Symbol Timing NCO
• Programmable I and Q, 256 Tap, Shaping FIR Filters with
Interpolation by 4, 8 or 16
• Interpolation Filter Up Samples Shaping Filter Output to
Output Sample Rate Under NCO Control
• Processing Capable of >90dB SFDR
• Cascade Input for Multiple Channel Transmissions
• 16-Bit µProcessor Interface for Configuration and User
Data Input
Applications
• Single or Multiple Channel Digital Software Radio
Transmitters (Wide-Band or Narrow-Band)
• Base Station Transceivers
• Operates with HSP50214 in Software Radio Solutions
• Compatible with the HI5741 D/A Converter
• HSP50215EVAL Evaluation Board Available
Ordering Information
PART
NUMBER
HSP50215VC
HSP50215VI
TEMP
RANGE (oC)
PACKAGE
PKG. NO
0 to 70 100 Ld MQFP Q100 .14x20
-40 to 85 s100 Ld MQFP Q100 .14x20
= µP CONTROL SIGNALS
GAIN
CTRL
++
OUT(15:0)
REFCLK
SYNCIN
RST
WR
RD
CE
C(15:0)
A(9:0)
MUX
FM
MOD
CONTROL
QIN(15:0)
IIN(15:0)
CF(31:0)
SF(29:0)
I FM
Q FM
NCO
NCO
CF(31:0)
OE
OFM
SYNCOUT
FIFORDY
SAMPCLK
3-422
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999




HSP50215VC pdf, 반도체, 판매, 대치품
HSP50215
Pin Descriptions
NAME
TYPE
VCC
GND
-
-
C(15:0)
I/O
A(9:0)
I
WR I
RD
CE
FIFORDY
REFCLK
CAS(15:0)
I
I
O
I
I
CASZ
I
OUT(15:0)
OFM
O
I
OE
SYNCIN
I
I
SYNCOUT
SAMPCLK
O
O
RST
I
DESCRIPTION
+5V Power supply input.
Power supply ground input.
µP Bidirectional Data bus. The C(15:0) bus is used for loading the configuration data and sample vectors for mod-
ulation. C15 is the MSB.
µP Address Bus. The A(9:0) bus is used for addressing the proper registers for loading the configuration data and
sample vectors for modulation. A9 is the MSB.
µP Write Strobe. When CE is asserted, data on the C(15:0) data bus is loaded into the address location found on
the A(9:0) bus on the rising edge of the WR signal. In some cases, there is an internal synchronization to the master
clock that must be completed before the next data is written. See the µP interface section for more information.
µP Read Control. When RD and CE are low, the data found in the address location defined by A(9:0) is routed to
the C(15:0) µP data bus on the next rising edge of REFCLK.
µP Chip Enable. Used to gate the WR and RD µP interface control signals.
FIFO Ready. A FIFORDY assertion indicates that the I and Q FIFOs have reached the programmed FIFO depth and
more samples are required to maintain that FIFO depth.
Reference Clock. REFCLK is the master clock for the DUC. All timing is relative to the REFCLK rising edge. The
frequency of the reference clock is denoted fCLK, and is the rate at which data is output from the part.
Cascade Input Bus. This input bus is used to cascade multiple parts by routing the digital modulated signal from
one DUC into the output summer of a second DUC. CAS(15:0) is 2’s complement format and is sampled on the
rising edge of REFCLK. CAS15 is the MSB.
Cascade Input Bus Zero. When CASZ is asserted (pulled high), the part places zeroes on the CAS(15:0) data path.
CASZ is asynchronous (not registered) to REFCLK and should not be changed on the fly. When unused, pull high
with a pull up resistor (~22k).
Output Data Bus. OUT(15:0) contains the digital modulated DUC output samples and is updated on the rising edge
of the REFCLK. OUT15 is the MSB.
Output Data Bus Format. When OFM is asserted (pulled high), the output bus format is 2’s complement. When not
asserted, the output format is offset binary. The OFM input is asynchronous (not registered) to REFCLK and should
not be changed on the fly.
Output Data Bus Enable. When OE is asserted (dropped low), the output data bus OUT(15:0) is enabled. When OE
is not asserted (pulled high), the output data bus OUT(15:0) is placed in the high impedance state.
Sync Input. The SYNCIN input is used to synchronize the processing of multiple parts. The SYNCOUT of one part
acts as a master and is connected to the SYNCIN of all of the DUC’s that are to by synchronized. The DUC can be
programmed so that either rising or falling edge of this signal initiates the processing.
Sync Output. The SYNCOUT output is used to synchronize the processing of multiple parts. The SYNCOUT of one
part acts as a master, and is connected to the SYNCIN of all of the DUC’s that are to be synchronized.
Sample Clock. This clock is provided to the data source to indicate when data is being transferred from the FIFO to
the shaping filter. The SAMPCLK output is generated by the sample rate NCO when the digital filter takes a new
sample. It has approximately 50% duty cycle. The sample is taken on the high-to-low transition. SAMPCLK may be
used instead of FIFORDY.
Reset. When the RST input is asserted (dropped low), the DUC is reset and all processing halts. The DUC may
also be reset on µP command. Processing remains halted until a sync is generated either by µP command or
assertion of SYNCIN. See the Reset section details of the specific functions halted by this control signal.
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HSP50215VC 전자부품, 판매, 대치품
HSP50215
of a quadrature NCO to produce a zero I.F. FM signal. These
FM modulated quadrature samples are then up sampled in
the interpolation filter to the output sample rate. The
baseband modulated signal is then upconverted to the
carrier frequency by the carrier NCO and mixers. The output
is then summed with the cascade input signal, saturated,
and formatted for output.
SHAPING
FM INTERPOLATION
I
FILTER
MODULATOR
FILTER
FIGURE 6. FM WITH PULSE SHAPING
In Mode 10, the amplitude out of the shaping filter needs to
be limited in order to prevent frequency excursions that
cannot be filtered out in the interpolation filter. The quality of
the FM signal is affected by the amplitude slew rate out of
the shaping filter. As a rule of thumb, limiting this slew rate to
less than 1/8 the sample rate will minimize this distortion.
FM Modulator
The FM modulator provides for frequency modulation of the
carrier center frequency by the PUC input data. The FM
modulator is driven either directly by the PUC I input (Mode
1) or by the output of the FIR shaping filter (Mode 2). The
input data to the FM Modulator, is defined as dφ(n)/dt, where
φ(nT) is the phase of a theoretical sinusoid described by:
s(n) = A (cos[φ(nT) ]+ j sin [φ(nT)]); A 1 in Modulator (EQ. 1)
Figure 7 illustrates the conceptual design of the FM modulator.
The input to the FM modulator, dφ(n)/dt, is integrated via the
carrier NCO accumulator. The NCO accumulator output
represents phase and is used to address a SIN/COS generator,
synthesizing a sinusoid of the form described in Equation 1.
The phase accumulator feedback of the NCO is 16 bits and
sixteen bits of the phase word are routed to the SIN/COS
generator. Sixteen bits of resolution are provided on the Sine
and Cosine outputs.
16
dφ(nT)/dt
EnNCO
MODE
1 OR 2
16
φ(nT)
16 COS[φ(nT)]
R 16 SIN[φ(nT)]
E
>G
FIGURE 7. FM MODULATOR BLOCK DIAGRAM
The transfer function of the FM modulator is defined by the
change in degrees per sample value, dφ(nT)/dt, where
dφ(nT)/dt is a 16-bit, twos complement, fractionally notated
frequency control word with a range from -FSAMP/2 to
+FSAMP/2. FSAMP is defined as the sample rate into FM
modulator. The maximum phase step that can occur in one
clock is ±180 degrees. Table 1 provides the change in phase
weighting of the input bits.
TABLE 1. FM MODULATOR TRANSFER FUNCTION
dφ(nT)/dt
DEGREES/SAMPLE
1000 0000 0000 0000
-180
0000 0000 0000 0000
0
0111 1111 1111 1111
~+180
Shaping Filter
The shaping filter provides the necessary pulse shaping
required on the input data to implement various quadrature
ASK and shaped FM modulation formats. Two identical
shaping filters (one each for the I and Q channels) are
provided. The filters can implement a 4-16 input sample
span impulse response using up to 256 taps with 16 bits of
resolution in the coefficients.
The range of valid digital values for the coefficients is from
8001 to 7FFF. The value 8000 is not allowed. The coefficient
format is 2’s complement. The span of the Impulse response
of the polyphase filter can be from 4-16 samples. The
desired sample span value minus one is programmed into
the Data Samples (DS) field in Control Word 19, bits 2-5.
The filter has a programmable interpolation rate (IP) of 4, 8,
or 16. This interpolation rate is programmed by Control
Address 19, bits 0 and 1. Thus, the required number of
coefficients (or filter span) becomes
# Coefficients = (DS)(IP)
(EQ. 2)
with 256 being the maximum number of coefficients.
Note that
REFCLK > (DS)(IP)(fS)
(EQ. 3)
where fS is the input sample rate of the shaping filter. For a
16 input sample impulse response span, the total impulse
response is 64, 128 or 256 filter taps for interpolation rates of
4, 8 or 16, respectively. The filter structure precludes
coefficient re-use for symmetric filters, so both asymmetric
and symmetric filters have up to 256 taps available and are
loaded in identical manner.
The maximum input sample rate is:
fS = fCLK [(IP)(DS) ]
(EQ. 4)
where fCLK is the frequency of the reference clock, IP is the
shaping filter interpolate rate; and DS is the number of data
samples in the filter span. For example, if fCLK = 52MHz, the
filter span is 16 samples, and the interpolation rate is 16,
then the maximum input sample rate, fS is 52/256 = 203kHz.
Table 2 shows several examples of calculations for FIR input
sample rates based on master reference clock rate, number
of data samples, and interpolation rate.
3-428

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부품번호상세설명 및 기능제조사
HSP50215VC

Digital UpConverter

Intersil Corporation
Intersil Corporation
HSP50215VI

Digital UpConverter

Intersil Corporation
Intersil Corporation

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