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PDF HSP50216 Data sheet ( Hoja de datos )
| Número de pieza | HSP50216 | |
| Descripción | Four-Channel Programmable Digital DownConverter | |
| Fabricantes | Intersil Corporation | |
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PRELIMINARY
Data Sheet
HSP50216
February 2000 File Number 4557.2
Four-Channel Programmable Digital
DownConverter
The HSP50216 Quad Programmable Digital DownConverter
(QPDC) is designed for high dynamic range applications
such as cellular basestations where multiple channel
processing is required in a small physical space. The QPDC
combines into a single package, a set of four channels which
include: digital mixers, a quadrature carrier NCO, digital
filters, a resampling filter, a Cartesian-to-polar coordinate
converter and an AGC loop.
The HSP50216 accepts four channels of 16-bit real digitized
IF samples which are mixed with local quadrature sinusoids.
Each channel carrier NCO frequency is set independently by
the microprocessor. The output of the mixers are filtered with
a CIC and FIR filters, with a variety of decimation options.
Gain adjustment is provided on the filtered signal. The digital
AGC provides a gain adjust range of up to 96dB with
programmable thresholds and slew rates. A cartesian to
polar coordinate converter provides magnitude and phase
outputs. A frequency discriminator provides a frequency
output via the FIR filter. Selectable outputs include I
samples, Q samples, Magnitude, Phase, Frequency and
AGC gain. The output resolution is selectable from 4-bit fixed
point to 32-bit floating point.
The maximum output bandwidth achievable using a single
channel is at least 1MHz.
Features
• Up to 70MSPS Input
• Four Independently Programmable Downconverter
Channels in a single package
• Four Parallel 16-Bit Inputs -Fixed or Floating Point Format
• 32-Bit Programmable Carrier NCO with > 115dB SFDR
• 110dB FIR Out of Band Attenuation
• Decimation from 8 to >65536
• 24-bit Internal Data Path
• Digital AGC with up to 96dB of Gain Range
• Filter Functions
- 1 to 5 Stage CIC Filter
- Halfband Decimation and Interpolation FIR Filter
- Programmable FIR Filter
- Resampling FIR Filter
• Cascadable Filtering for Additional Bandwidth
• Four Independent Serial Outputs
• 3.3V Operation
Applications
• Narrow-Band TDMA through IS-95 CDMA Digital Software
Radio and Basestation Receivers
Ordering Information
PART
NUMBER
HSP50216KI
TEMP
RANGE (oC)
PACKAGE
-40 to +85 196 Ld BGA
PKG. NO
V196.12x12
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FOR MORE INFORMATION CONTACT: JUAN GARCIA - 321-729-5883 | Copyright © Intersil Corporation 2000
1 page  
HSP50216
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
SYNCB
O Serial Data Output 1B sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCB is programmable.
SYNCC
O Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCC is programmable.
SYNCD
O Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCD is programmable.
MICROPROCESSOR INTERFACE
P(15:0)
I/O Microprocessor Interface Data bus. See Microprocessor Interface Section. P15 is the MSB.
ADD(2:0)
I Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section. Note:
ADD2 is not used but designated for future expansion.
WR I Microprocessor Interface Write Signal. The data on P(15:0) is written to the destination selected by
ADD(2:0) on the rising edge of WR when CE is asserted (low). See Microprocessor Interface Section.
RD I Microprocessor Interface Read Strobe. The data at the address selected by ADD(2:0) is placed on
P(15:0) when RD is asserted (low) and CE is asserted (low). See Microprocessor Interface Section.
µP MODE
I Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the
Microprocessor Interface.
CE I Microprocessor Interface Chip Select. Active low. This pin has the same timing as the address pins.
INTRPT
O Microprocessor Interrupt Signal. Asserted for a programmable number of clock cycles when new data is
available on the selected Channel.
Functional Description
The HSP50216 is a four channel digital receiver integrated
circuit offering exceptional dynamic range and flexibility.
Each of the four channels consists of a front-end NCO/digital
mixer/CIC-filter block and a back-end FIR/AGC/polar-
conversion block. The parameters for the four channels are
independently programmable. Four parallel data input
busses (A(15:0), B(15:0), C(15:0) and D(15:0)) and four
serial data outputs (SDxA, SDxB, SDxC, and SDxD; x = 1 or
2) are provided. Each input can be connected to any or all of
the internal signal processing channels, Channels 0, 1, 2
and 3. The output of each channel can be routed to any of
the serial outputs. Outputs from more than one channel can
be multiplexed through a common output if the channels are
synchronized. The four channels share a common input
clock and a common serial output clock, but the output
sample rates can be synchronous or asynchronous. Bus
multiplexers between the front end and back end sections
provide flexible routing between channels for cascading
back-end filters or for routing one front end to multiple back
ends for polyphase filtering (to provide wider bandwidth
filtering). A level detector is provided to monitor the signal
level on any of the parallel data input busses.
Each front end NCO/digital mixer/CIC filter section includes
a quadrature numerically controlled oscillator (NCO), digital
mixer, and a cascaded-integrator-comb filter (CIC). The
NCO has a 32-bit frequency control word for 16.3MHz tuning
resolution at an input sample rate of 70MSPS. The SFDR of
the NCO is >115dB. The CIC filter order is programmable
between 1 and 5 and the CIC decimation factor can be
programmed from 4 to 65536, depending on the number of
stages selected.
Each back end section includes an FIR processing block, an
AGC and a cartesian-to-polar coordinate converter. The FIR
processing block is a flexible filter compute engine that can
compute a single FIR or a set of filters. A single filter in a
chain can have up to 256 taps and the total number of taps
in a set of filters can be up to 384. The filter compute engine
supports a variety of filter types including decimation,
interpolation and resampling filters. The coefficients for the
programmable digital filters are 22 bits wide. Coefficients are
provided in ROM for several halfband filter responses and for
a resampler. The AGC section can provide up to 96dB of
either fixed or automatic gain control. For automatic gain
control, two settling modes and two sets of loop gains are
provided. Separate attack and decay slew rates are provided
for each loop gain. Programmable limits allow the user to
select a gain range less than 96dB. The outputs of the
cartesian-to-polar coordinate conversion block, used by the
AGC loop, are also provided as outputs to the user for
demodulation.
The HSP50216 supports both fixed and floating point
parallel data input modes. The floating point modes support
gain ranging A/D converters. Gated, interpolated and
multiplexed data input modes are supported. The serial data
output word width for each data type can be programmed to
one of ten output bit widths from 4-bit fixed point through 32-
bit IEEE floating point.
5
5 Page 
HSP50216
bursts (as when computing interpolation filters). The FIFO is
four samples deep. The FIFO is loaded by the output of the
filter when that path is selected. It is unloaded by a counter.
The spacing of the output samples is specified in clock
periods. The spacing can be from 1 (fall through) to 4096
samples (approximately the spacing for a 16KSPS output
sample rate when using 65MSPS clock).
The number and order of the filtering in the filter chain is
defined by a FIR control program. The FIR control program
is a sequence of up to 32 instruction words. Each instruction
word can be a filter or program flow instruction. The filter
instruction defines a FIR in the chain, specifying the type of
FIR, number of taps, decimation, memory allocation, etc. For
program flow, a wait for input sample(s) instruction, a loop
counter load, and several jumps (conditional and
unconditional) are provided.
The simplest filter program computes a single filter. It has
three instructions (see Sample Filter #1Program Instructions
below):
SAMPLE FILTER #1 PROGRAM
STEP
INSTRUCTION
0 Wait for enough input samples
(equal to the decimation factor)
1 FIR
Type = even symmetric
95 taps
Dec x 2
Compute one output
Decrement wait counter
Memory block size 128
Memory block start at 64,
Coefficient block start at 64
Step size 1
Output to AGC
2 Jump, Unconditional, to step 0
The parameters of the FIR (including type, number of taps,
decimation and memory usage) are specified in the bit fields
of the step 2 instruction word. To change the filtering the only
other change needed is the number of samples in the wait
threshold register. The filter in this example requires 52 clock
cycles to compute, allocated as follows:
SAMPLE FILTER #1 CLOCK CYCLES CALCULATION
CLOCK
CYCLES
FUNCTION PERFORMED
48 Clocks for FIR computation (two taps/clock due to
symmetry)
2 Clocks for writing the input data into the data RAMs
(Decimate by 2 requires 2 inputs per output)
2 Clocks for the program flow instructions (wait and
jump)
52 Total
Using a 65MSPS clock, the output sample rate could be as
high as 1.25MSPS. The input sample rate from the CIC filter
would be 2.5MSPS. The impulse response length would be
38 µsec (95 taps at 0.4µs/tap).
Each additional filter added to the signal processing chain
requires one instruction step. As an example of this, a typical
filter chain might consist of two decimate-by-2 halfband
filters being followed by a shaping filter with the final filter
being a resampling filter. The program for this case might be
(see Sample Filter Program #2 Instructions below):
SAMPLE FILTER #2 PROGRAM
STEP
INSTRUCTION
0 Wait for enough input samples (usually equal to the
total decimation - 8 in this case)
1 FIR
Type = even symmetry
15 taps
Halfband
Dec x 2
Compute four outputs
Memory block size 32
Memory block start at 0
Coefficient block start at 13
Output to step 2
Decrement wait count
2 FIR
Type = even symmetry
23 taps
Halfband
Dec x 2
Compute two outputs
Memory block size 32
Memory block start at 32
Coefficient block start at 24
Output to step 3
3 FIR
Type = even symmetry
95 taps
Dec x 2
Compute one output
Memory block size 128
Memory block start at 64
Coefficient block start at 64
Step size 1
Output to step 4
4 FIR
Type = resampler
Increment NCO
6 taps
Compute one output
Memory block size 8
Memory block starts at 192
Coefficient block start at 512
Step size 32
Output to AGC
5 Jump, Unconditional, to 0
11
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| PDF Descargar | [ Datasheet HSP50216.PDF ] | |
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