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PDF HSP50306SC-27 Data sheet ( Hoja de datos )
| Número de pieza | HSP50306SC-27 | |
| Descripción | Digital QPSK Demodulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HSP50306
February 1998
Digital QPSK Demodulator
Features
• 25.6MHz or 26.97MHz Clock Rates
• Single Chip QPSK Demodulator with 10kHz Tracking
Loop
• Square Root of Raised Cosine (α = 0.4) Matched
Filtering
• 2.048 MBPS Reconstructed Output Data Stream
• Bit Synchronization with 3kHz Loop Bandwidth
• Internal Equalization for Multipath Distortion
• 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF
• Level Detection for External IF AGC Loop
• 0.1s Acquisition Time
• 10-9 BER
• <116mA on +5.0V Supply
Applications
• Cable Data Link Receivers
• Cable Control Channel Receivers
Ordering Information
PART NUMBER
TEMP.
RANGE (oC) PACKAGE
PKG.
NO.
HSP50306SC-27
0 to 70 16 Ld SOIC M16.3
HSP50306SC-2796
0 to 70 Tape and Reel
HSP50306SC-25
0 to 70 16 Ld SOIC M16.3
HSP50306SC-2596
0 to 70 Tape and Reel
Description
The HSP50306 is a 6-bit QPSK demodulator chip designed
for use in high signal to noise environments which have some
multipath distortion. The part recovers 2.048 MBPS data from
samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.
The chip coherently demodulates the waveform, recovers
symbol timing, adaptively equalizes the signal to remove
multipath distortion, differentially decodes and multiplexes the
data decisions. 8-A lock signal is provided to indicate when
the tracking loops are locked and the data decisions are valid.
To optimize performance, a gain error feedback signal is
provided which can be filtered and used to close an I.F. AGC
loop around the A/D converter.
The QPSK demodulator derives all timing from CLKIN. The
chip divides this clock by 2 to provide the sample clock for the
external A/D converter. The -27 version operates at a clock
input of 26.97MHz and demodulates a 10.7MHz QPSK signal
to recover the 2048 KSPS data. The -25 version operates at a
clock input of 25.6MHz and demodulates a 2.1MHz QPSK
signal to recover the 2048 KSPS data. Variation from these
CLKIN frequencies will progressively degrade the receive
data rate, the receive IF, acquisition sweep rate, acquisition
sweep range and loop bandwidths as the deviation increases
from normal CLKIN. Details on the maximum allowable devia-
tion are found in the Input Characteristics section. The
HSP50306 processes 6-bit offset binary data. 4-bit data pro-
vides adequate performance for many applications.
Block Diagram
I
DIN0-5
AGCOUT
ADCLK
CLKIN
RESET
TEST
6
COS SIN
LEVEL
DETECT
NCO
CARRIER
LOOP FILTER
Q
BIT PHASE
DETECTOR
TIMING
GENERATOR
BIT SYNC
LOOP FILTER
4 TAP
ADAPTIVE
EQUALIZER
I DIFF.
Q DECODE/
MUX
CARRIER
PHASE
DETECT
LOCK
DETECT
DATAOUT
LOCK
CLKOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
8-272
File Number 4162.2
1 page  
HSP50306
Two Versions: Different Applications
The -27 and -25 versions of the HSP50306 Digital QPSK
Demodulator are not simply different speed grades of the
same device, but are designs which have proportionally
scaled clocks and bandwidths for different applications.
NOTE: While these parts are pin for pin compatible, in
most applications they cannot be used as functional
equivalent substitutes for each other. Key differences are:
• The -27 version of the HSP50306 has an input IF of
10.7MHz with an input clock of 26. 97MHz.
• The -25 version of the HSP50306 has an input IF of
2.1MHz with an input clock of 25. 6MHz.
RECEIVE IF
DEMOD INPUT IF
DC 2.79
10.7 FS 16.27
24.19 FCLK 29.76
FIGURE 3. SAMPLED SPECTRUM FOR THE -27 VERSIONS
(fCLK = 26.97MHz)
DEMOD INPUT IF RECEIVE IF
In both the -27 and -25 designs, the sample rate clock for the
input IF signal is half of the CLK frequency. NOTE: Sample
rate clock is designated by fS = fCLK/2. Aside from input
IF and input clock, all other performance parameters of the
two parts are identical for their respective IF inputs.
DC 2.1
10.7 FS 14.9
23.5 FCLK 27.7
FIGURE 4. SAMPLED SPECTRUM FOR THE -25 VERSIONS
(fCLK = 25.6MHz)
10.7MHz Input IF Applications
Both the -27 and -25 parts can be used in 10.7MHz IF Applica-
tions. Figures 3 and 4 show the frequency spectrum for the
sampled 10.7MHz IF input signals for both the -27 and -25 ver-
sions, respectively. In the 10.7MHz IF Application, the -25 ver-
sion offers tighter filtering capability than the -27 version
because the lower IF allows use of low pass filtering. Also, the
lower IF of the -25 version has inherently lower internal pro-
cessing spectral spurs than the -27 version. Note that the
receive IF for the HSP50306SC-27 is the input IF to the demod-
ulator. For the HSP50306SC-25, the receive IF is 10.7MHz, but
the processing is done on the spectral image at 2.1MHz. Exam-
ine the spectral inversion between the 10.7MHz Receive IF and
the 2.1MHz demodulator input in Figure 4. The transmit differ-
ential encoder must take into account this spectral rever-
sal. The required encoding is shown in Table 3. This part was
designed to be paired with the HSP50307 Burst Modulator, and
can be operated from the same 25.6MHz reference clock.
TABLE 3. DIFFERENTIAL ENCODING REQUIRED FOR THE -27
AND -25 DEMODULATORS RECEIVING 10.7MHz IF
INPUT
BITS
PHASE CHANGE
REQUIRED FOR -27
DEMODULATION
PHASE CHANGE
REQUIRED FOR -25
DEMODULATION
00 0o
0o
01 -90o
90o
10 90o
-90o
11 180o
180o
8-276
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| PDF Descargar | [ Datasheet HSP50306SC-27.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HSP50306SC-25 | Digital QPSK Demodulator | Intersil Corporation |
| HSP50306SC-2596 | Digital QPSK Demodulator | Intersil Corporation |
| HSP50306SC-27 | Digital QPSK Demodulator | Intersil Corporation |
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