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PDF HSP50307SC Data sheet ( Hoja de datos )
| Número de pieza | HSP50307SC | |
| Descripción | Burst QPSK Modulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HSP50307
December 1996
Burst QPSK Modulator
Features
• 256 KBPS Data Rate and 128 KBPS Baud Rate
• Burst QPSK Modulation
• Programmable Carrier Frequency from 8MHz to
15MHz With a Frequency Step Size of 32kHz
• α = 0.5 Root Raised Cosine (RRC) Filtering For Spec-
trum Shaping
• On-Board Synthesizer
• Programmable Output Level From 22 to 62dBmV in
1dB Steps
• Programmable Charge Pump Current Control
• 62dBmV Differential Output Driver for 75Ω Cable
Applications
• Burst QPSK Modulator
• HSP50307EVAL1 Evaluation Board Is Available
Ordering Information
PART NUMBER
HSP50307SC
TEMP.
RANGE (oC)
PACKAGE
0 to 70
28 Ld SOIC
PKG.
NO.
M28.3
Description
The HSP50307 is a mixed signal burst QPSK Modulator for
upstream CATV Applications. The HSP50307 demultiplexes
and modulates a serial data stream onto an RF Carrier cen-
tered between 8 and 15MHz. The signal spectrum is shaped
with α = 0.5 root raised cosine (RRC) digital filters. On-chip fil-
tering limits spurs and harmonics to levels below -35dBc dur-
ing transmissions. The output power level is adjustable over a
40dB range in 1dB steps. The maximum differential output
level is +62dBmV into 75Ω. A transmitter inhibit function dis-
ables the RF output outside the burst interval. The differential
output amplifier int7-erfaces to the cable via a transformer.
The Block Diagram of the HSP50307 QPSK Modulator is
shown below. The HSP50307 consists of a digital control
interface, an I/Q generator, a synthesizer, and a quadrature
modulator.
The data clock is derived from the master clock. The
HSP50307 demultiplexes the input data bits into in-phase (I)
and quadrature (Q) data streams. The first bit and subsequent
alternating bits of the burst are in-phase data. The two data
streams are filtered, converted from digital to analog, and low
pass filtered to produce the baseband I and Q analog signals.
The baseband signals are up-converted to RF in the Quadra-
ture Modulation Section. The synthesizer provides the local
oscillator (LO) for the quadrature modulator. The frequency is
programmable via the control interface with a resolution of
32kHz. The output of the quadrature modulator is low pass fil-
tered to remove harmonic distortion.
Block Diagram
RCLK VCO_IN VCO_SET PD_OUT
RESET
CCLK
C_EN
CDATA
TX_EN
TX_DATA
TXCLK
MCLK
CONTROL
INTERFACE
†
SYNTHESIZER
I/Q GENERATOR
I
9
8RRC
D/A
†
LPF
Q9
8RRC
D/A
LPF
/100
QUAD
GEN
QUADRATURE
MODULATOR
†
+ LPF PGA
TX_EN
MOD_OUT-
MOD_OUT+
† Indicates analog circuitry.
DAC_REF
MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
7-68
VCM_REF
File Number 4219
1 page  
Applications Example
25.6MHz
OSC
HSP50307
+5VDIGITAL
0.1µF
DGND
DATA
SOURCE
+5VANALOG
DGND
0.1µF
1 MCLK
2 TXCLK
CCLK 28
CDATA 27
CONTROL
PROC.
3 TX_EN
C_EN 26
4 TX_DATA
5 RESET
6 DGND
7 AVCC
8 AGND
9 IBBOUT
DVCC 25
RCLK 24
AGND 23
PD_OUT 22
VCO_IN 21
VCO_SET 20
2.048MHz
OSC
2kΩ
100pF
0.01µF
+5VANALOG
6.25kΩ 0.01µF
10 QBBOUT
AVCC 19
11 QBBIN
0.1µF
12 IBBIN
0.1µF
13 DAC_REF
0.1µF
14 VCM_REF
0.1µF
MOD_OUT- 18
MOD_OUT+ 17
AVDD 16
AGND 15
CABLE
37.5Ω 0.1µF TRANSFORMER
RFOUT
37.5Ω 0.1µF
+9VANALOG
0.1µF
AGND
AGND
FIGURE 4. APPLICATIONS EXAMPLE OF THE HSP50307
Figure 4 shows an applications example of the HSP50307.
The MCLK source operates at 25.6MHz, and the RCLK
operates at 2.048MHz. 0.1µF capacitors are connected from
the IBBOUT to IBBIN and the QBBOUT to QBBIN, providing
AC coupling to the Analog Upconverter Section of the
HSP50307.
The control processor sends the 23-bit control word via the
three-wire interface. The data source receives the 256kHz
TXCLK from the HSP50307 and transmits data and enable
signal at the 256kHz rate.
The DAC_REF and VCM_REF are connected to 0.1µF
capacitors to ground. Each of the differential drivers are
loaded with a 37.5Ω resistor and a 0.1µF capacitor. The
37.5Ω resistors provide matching to the 75Ω cable. The
capacitors perform AC coupling. The drive paths are sent to
the cable transformer for data transmissions.
Table 3 shows the general functional specifications for the
applications example shown in Figure 4. It gives an overview
of what is being accomplished but does not specify an exact
carrier frequency or other programmable functions. These
specifications are met given a valid control word combination
and the applications circuit shown in Figure 4. Table 4 sum-
marizes the performance of the applications example shown
in Figure 4. Again, these specifications are met given a valid
programmed mode.
NOTE: The HSP50307 is sensitive to layout. Users must
make sure the input signals do not couple back into the
output signals. The performance of the HSP50307 is
also sensitive to the decoupling capacitors between
1) QBBOUT and QBBIN and 2) IBBOUT and IBBIN. The
values shown in Figure 4 are recommended.
7-72
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