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PDF HT49C30L Data sheet ( Hoja de datos )
| Número de pieza | HT49C30L | |
| Descripción | 8-Bit LCD Type MCU | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT49R30A-1/HT49C30-1/HT49C30L
8-Bit LCD Type MCU
Features
· Operating voltage:
2.2V~5.5V for HT49R30A-1/HT49C30-1
1.2V~2.2V for HT49C30L
· 6 input lines
· 8 bidirectional I/O lines
· Two external interrupt input
· One 8-bit programmable timer/event counter with
PFD (programmable frequency divider) function
· LCD driver with 19´2, 19´3 or 18´4 segments
· 2K´14 program memory ROM
· 96´8 data memory RAM
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 4-level subroutine nesting
· Bit manipulation instruction
· 14-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
for HT49R30A-1/HT49C30-1
· Up to 8ms instruction cycle with 500kHz system clock
for HT49C30L
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· Low voltage reset/detector for
HT49R30A-1/HT49C30-1
· 48-pin SSOP package
General Description
The HT49C30-1 and the HT49C30L are 8-bit high per-
formance single chip microcontrollers. The
HT49R30A-1 is the OTP version of the HT49C30-1. Its
single cycle instruction and two-stage pipeline architec-
ture make it suitable for high speed applications. The
devices are also suitable for use in multiple LCD low
power applications such as scales, leisure products,
high-level household appliances, hand held LCD prod-
ucts and batteries operated systems in particular.
Rev. 1.10
1 September 25, 2002
1 page  
HT49R30A-1/HT49C30-1/HT49C30L
Pad Name
OSC4
OSC3
VDD
OSC2
OSC1
RES
I/O Options
Description
O
I
RTC or
System Clock
Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purposes or to a system clock source (depending
on the options).
¾ ¾ Positive power supply
OSC1 and OSC2 are connected to an RC network or a crystal (by options)
O
I
for the internal system clock. In the case of RC operation, OSC2 is the output
Crystal or RC terminal for 1/4 system clock.
The system clock may come from the RTC oscillator. If the system clock co-
mes from RTCOSC, these two pins can be floating.
I ¾ Schmitt trigger reset input, active low
Absolute Maximum Ratings
Supply Voltage..................................VSS-0.3V to 5.5V*
Storage Temperature ............................-50°C to 125°C
Operating Temperature ...........................-40°C to 85°C
Supply Voltage ................................VSS-0.3V to 2.2V**
Input Voltage..............................VSS-0.3V to VDD+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
²*² For HT49R30A-1/HT49C30-1
²**² For HT49C30L
D.C. Characteristics
VDD=1.5V for HT49C30L, VDD=3V & VDD=5V for HT49R30A-1 and HT49C30-1
Symbol
Parameter
VDD Operating Voltage
Test Conditions
VDD Conditions
for HT49C30L
¾ LVR disable
(for HT49R30A-1/HT49C30-1)
IDD1
Operating Current
(Crystal OSC)
1.5V No load, fSYS=455kHz
3V
No load, fSYS=4MHz
5V
IDD2
Operating Current
(RC OSC)
1.5V No load, fSYS=400kHz
3V
No load, fSYS=4MHz
5V
IDD3
Operating Current
(fSYS=32768Hz)
1.5V
3V No load
5V
ISTB1
Standby Current
(*fS=T1)
1.5V
3V
No load, system HALT,
LCD off at HALT
5V
Ta=25°C
Min. Typ. Max. Unit
1.2 ¾ 2.2 V
2.2 ¾ 5.5 V
¾ 60 100 mA
¾1
2 mA
¾3
5 mA
¾ 50 100 mA
¾1
2 mA
¾3
5 mA
¾ 2.5 4 mA
¾ 0.3 0.6 mA
¾2
4 mA
¾ 0.1 0.5 mA
¾ ¾ 1 mA
¾ ¾ 2 mA
Rev. 1.10
5 September 25, 2002
5 Page 
HT49R30A-1/HT49C30-1/HT49C30L
The ALU not only saves the results of a data operation
but also changes the status register.
Status register - STATUS
The status register (0AH) is of 8 bits wide and contains,
a carry flag (C), an auxiliary carry flag (AC), a zero flag
(Z), an overflow flag (OV), a power down flag (PD), and
a watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except the TO and PD flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PD flags. Operations related to the status register,
however, may yield different results from those in-
tended. The TO and PD flags can only be changed by a
Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruc-
tion. The Z, OV, AC, and C flags reflect the status of the
latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Interrupts
The device provides two external interrupts, an internal
timer/event counter interrupt, an internal time base in-
terrupt, and an internal real time clock interrupt. The in-
terrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the PC onto the stack followed
by a branch to a subroutine at the specified location in
the ROM. Only the contents of the PC is pushed onto
the stack. If the contents of the register or of the status
register (STATUS) is altered by the interrupt service pro-
gram which corrupts the desired control sequence, the
contents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT0 or INT1, and the related interrupt request
flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as
well. After the interrupt is enabled, the stack is not full,
and the external interrupt is active, a subroutine call to
location 04H or 08H occurs. The interrupt request flag
(EIF0 or EIF1) and EMI bits are all cleared to disable
other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 6 of INTC0), which is normally caused by a timer
overflow. After the interrupt is enabled, and the stack is
Labels
C
AC
Z
OV
PD
TO
¾
¾
Bits Function
C is set if the operation results in a carry during an addition operation or if a borrow does not take
0 place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PD is cleared by either a system power-up or executing the ²CLR WDT² instruction. PD is set by
executing the ²HALT² instruction.
5
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6 Unused bit, read as ²0²
7 Unused bit, read as ²0²
Status register
Rev. 1.10
11 September 25, 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT49C30L.PDF ] | |
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