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부품번호 HUF75842S3S 기능
기능 43A/ 150V/ 0.042 Ohm/ N-Channel/ UltraFET Power MOSFET
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HUF75842S3S 데이터시트, 핀배열, 회로
Data Sheet
HUF76009P3, HUF76009D3S
December 2001
20A, 20V, 0.027 Ohm, N-Channel, Logic
Level Power MOSFETs
THE HUF76009 is an application-specific MOSFET
optimized for switching when used as the upper switch in
synchronous buck applications. The low gate charge and low
input capacitance results in lower driver and lower switching
losses thereby increasing the overall system efficiency.
Symbol
D
G
S
Packaging
HUF76009D3S
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
HUFD76009P3
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
Features
• 20A, 20V
- rDS(ON) = 0.027Ω, VGS = 10V
- rDS(ON) = 0.039Ω, VGS = 5V
• PWM optimized for synchronous buck applications
• Fast Switching
• Low Gate Charge
- Qg Total 11nC (Typ)
• Low Capacitance
- CISS 470pF (Typ)
- CRSS 50pF (Typ)
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76009P3
TO-220AB
76009P
HUF76009D3S
TO-252AA
76009D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the HUF76009D3S in tape and reel, e.g., HUF76009D3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
SYMBOL
PARAMETER
HUF76009P3,
HUF76009D3S
UNITS
VDSS
VDGR
VGS
ID
ID
IDM
PD
Drain to Source Voltage (Note 1)
Drain to Gate Voltage (RGS = 20k) (Note 1)
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2)
Continuous (TC = 100oC, VGS = 5V)
Pulsed Drain Current
Power Dissipation
Derate Above 25oC
TJ, TSTG
Operating and Storage Temperature
Maximum Temperature for Soldering
TL
Tpkg
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
THERMAL SPECIFICATIONS
RθJC
RθJA
Thermal Resistance Junction to Case, TO-220, TO-252
Thermal Resistance Junction to Ambient TO-220
Thermal Resistance Junction to Ambient TO-252
20
20
±16
20
16
Figure 4
41
0.33
-55 to 150
300
260
3.04
62
100
V
V
V
A
A
A
W
W/oC
oC
oC
oC
oC/W
oC/W
oC/W
NOTE:
1. TJ = 25oC to 125oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B




HUF75842S3S pdf, 반도체, 판매, 대치품
HUF76009P3, HUF76009D3S
Typical Performance Curves (Continued)
200
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
SINGLE PULSE
TJ = MAX RATED TC = 25oC
1
1
10
1ms
10ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
50
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
30
20
10
0
2
TJ = 150oC
TJ = 25oC
TJ = -55oC
34
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 6. TRANSFER CHARACTERISTICS
5
40
VGS = 10V
30
20
VGS = 5V
VGS = 4.5V
TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 4V
10 VGS = 3.5V
VGS = 3V
0
0123
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
60
PULSE DURATION = 80µs
ID = 16A
DUTY CYCLE = 0.5% MAX
50 TC = 25oC
ID = 5A
40
ID = 10A
30
20
10
2
468
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
0.6
-80
VGS = 10V, ID = 20A
-40 0
40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
VGS = VDS, ID = 250µA
1.0
0.8
0.6
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B

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HUF75842S3S 전자부품, 판매, 대치품
HUF76009P3, HUF76009D3S
PSPICE Electrical Model
.SUBCKT HUF76009P3 2 1 3 ; rev 16 March 2000
CA 12 8 5.6e-10
CB 15 14 5.0e-10
CIN 6 8 4.5e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 25.9
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.6e-9
LSOURCE 3 7 4.7e-9
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.0e-3
RGATE 9 20 4.0
RLDRAIN 2 5 10
RLGATE 1 9 46
RLSOURCE 3 7 47
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.4e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
DPLCAP 5
10
RSLC2
RSLC1
51
5
51
ESLC
DBREAK
11
LDRAIN
DRAIN
2
RLDRAIN
-
LGATE
ESG
6
8
+ EVTHRES
+ 19 -
EVTEMP
8
RGATE + 18 - 6
9 20 22
RLGATE
CIN
S1A
12 13
8
S2A
14
13
15
50
RDRAIN
16
21
EBREAK
+
17
18
-
MWEAK
DBODY
MMED
MSTRO
87
RSOURCE
LSOURCE
SOURCE
3
RLSOURCE
RBREAK
17 18
S1B
S2B
CA 13 CB
+ + 14
EGS
6
8
-
EDS
5
8
-
RVTEMP
19
IT -
VBAT
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),3))}
.MODEL DBODYMOD D (IS = 3.4e-13 RS = 1.0e-2 TRS1 = 2e-3 TRS2 = 8e-7 CJO = 1.05e-9 TT = 1.18e-8 XTI = 5 M = 0.42)
.MODEL DBREAKMOD D (RS = 1.3e- 1TRS1 = 0TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 3.2e-1 0IS = 1e-3 0N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 2.38 KP = 12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RS = 0.03 RG = 4)
.MODEL MSTROMOD NMOS (VTO = 2.87 KP = 28 LAMBDA = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.95 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.7e- 4TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 9.8e-3 TC2 = 2.85e-5)
.MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 5.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.48e-3 TC2 = -5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.68e- 3TC2 = 8e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.7 VOFF= -2.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= -4.7)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0.3)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B

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