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PDF HUF76113T3ST Data sheet ( Hoja de datos )

Número de pieza HUF76113T3ST
Descripción 4.7A/ 30V/ 0.031 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFET
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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TM
Data Sheet
HUF76113T3ST
June 2000 File Number 4388.3
4.7A, 30V, 0.031 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
This N-Channel power MOSFET is
® manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery-
operated products.
Formerly developmental type TA76113.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76113T3ST
SOT-223
76113
NOTE: HUF76113T3ST is available only in tape and reel.
Features
• Logic Level Gate Drive
• 4.7A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.031
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER™ Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
DRAIN
(FLANGE)
SOT-223
SOURCE
DRAIN
GATE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Intersil Corporation.
PSPICE® is a registered trademark of MicroSim Corporation. SABER™ is a trademark of Analogy, Inc.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

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HUF76113T3ST pdf
HUF76113T3ST
Typical Performance Curves (Continued)
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
25 VDD = 15V
20
15
10
5
0
0
150oC
25oC
-55oC
1234
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
5
30
25
VGS = 10V
VGS = 5V
VGS = 4V
20 VGS = 3.5V
15
10
5
0
0
VGS = 3V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
123
VDS, DRAIN TO SOURCE VOLTAGE (V)
4
FIGURE 8. SATURATION CHARACTERISTICS
80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
70
60
ID = 4.7A
50
40
ID = 0.5A
30
20
2
468
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.2
VGS = VDS, ID = 250µA
1.1
1.0
0.9
0.8
0.7
0.6
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1.8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.6 VGS = 10V, ID = 4.7A
1.4
1.2
1.0
0.8
0.6
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
ID = 250µA
1.1
1.0
0.9
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
5

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HUF76113T3ST arduino
HUF76113T3ST
SPICE Thermal Model
REV August 1998
HUF76113T3ST
Copper Area = 0.077 in2
CTHERM1 th 8 1.9e-5
CTHERM2 8 7 9.5e-4
CTHERM3 7 6 1.9e-3
CTHERM4 6 5 3.5e-3
CTHERM5 5 4 2.0e-2
CTHERM6 4 3 6.5e-2
CTHERM7 3 2 2.4e-1
CTHERM8 2 tl 9.0e-1
RTHERM1 th 8 3.5e-3
RTHERM2 8 7 3.1e-2
RTHERM3 7 6 2.0e-1
RTHERM4 6 5 8.0e-1
RTHERM5 5 4 2.1
RTHERM6 4 3 11
RTHERM7 3 2 32
RTHERM8 2 tl 66
th JUNCTION
RTHERM1
RTHERM2
RTHERM3
RTHERM4
8
7
6
5
CTHERM1
CTHERM2
CTHERM3
CTHERM4
SABER Thermal Model
Copper Area = 0.077 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.9e-5
ctherm.ctherm2 8 7 = 9.5e-4
ctherm.ctherm3 7 6 = 1.9e-3
ctherm.ctherm4 6 5 = 3.5e-3
ctherm.ctherm5 5 4 = 2.0e-2
ctherm.ctherm6 4 3 = 6.5e-2
ctherm.ctherm7 3 2 = 2.4e-1
ctherm.ctherm8 2 tl = 9.0e-1
rtherm.rtherm1 th 8 = 3.5e-3
rtherm.rtherm2 8 7 = 3.1e-2
rtherm.rtherm3 7 6 = 2.0e-1
rtherm.rtherm4 6 5 = 8.0e-1
rtherm.rtherm5 5 4 = 2.1
rtherm.rtherm6 4 3 = 11
rtherm.rtherm7 3 2 = 32
rtherm.rtherm8 2 tl = 66
}
COMPONENT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.077 in2
6.5e-2
2.4e-1
9.0e-1
11
32
66
RTHERM5
RTHERM6
RTHERM7
RTHERM8
4
3
2
CTHERM5
CTHERM6
CTHERM7
CTHERM8
tl AMBIENT
TABLE 1. THERMAL MODELS
0.308 in2
0.535 in2
6.7e-2
6.7e-2
3.5e-1
3.5e-1
1.7 1.9
99
18 16
45.5 40
0.76 in2
6.7e-2
3.5e-1
2
9
15.5
36
0.996 in2
6.7e-2
3.5e-1
2.4
9
14.5
31.5
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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